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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 6, Issue 3, May 2012

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Volume 6, Issue 3

May 2012

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    • Machine learning predictive modelling high-level synthesis design space exploration
      • Author(s): B. Carrion Schafer  and  K. Wakabayashi
      • Source: IET Computers & Digital Techniques, Volume 6, Issue 3, p. 153 –159
      • DOI:  10.1049/iet-cdt.2011.0115
      • Type: Article
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      • p. 153 –159 (7)
        A machine learning-based predictive model design space exploration (DSE) method for high-level synthesis (HLS) is presented. The method creates a predictive model for a training set until a given error threshold is reached and then continues with the exploration using the predictive model avoiding time-consuming synthesis and simulations of new configurations. Results show that the authors’ method is on average 1.92 times faster than a genetic-algorithm DSE method generating comparable results, whereas it achieves better results when constraining the DSE runtime. When compared with a previously developed simulated annealer (SA)-based method, the proposed method is on average 2.09 faster, although again achieving comparable results.
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      Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation
      • Author(s): A. Lopes Filho  and  R. d'Amore
      • Source: IET Computers & Digital Techniques, Volume 6, Issue 3, p. 160 –165
      • DOI:  10.1049/iet-cdt.2011.0056
      • Type: Article
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      • p. 160 –165 (6)
        The successful use of commercial-off-the-shelf (COTS) devices on board space applications requires the use of fault mitigation methods because of the effects of space radiation in microelectronics devices. This study describes a scheme for the random injection of single event transients/upsets to evaluate the viability of employing COTS field programmable gate array for an onboard, low-complexity, remote-sensing image data compressor. The fault injection features are added to the application to be tested by modifying its hardware description language source code. Then the tests are executed by simulation, with or without the inclusion of fault mitigation methods, so that comparative evaluations can be quickly obtained. The evaluation results (robustness enhancement against area) of different fault mitigation methods are presented, with good estimates of the behaviour of the hardware implementation of the application in a space radiation environment.
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      Evaluation of testability enhancement using software prototype
      • Author(s): E. Bareisa ; V. Jusas ; K. Motiejunas ; R. Seinauskas
      • Source: IET Computers & Digital Techniques, Volume 6, Issue 3, p. 166 –172
      • DOI:  10.1049/iet-cdt.2011.0095
      • Type: Article
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      • p. 166 –172 (7)
        The functional delay-fault models, which are based on the input stimuli and correspondent responses at the outputs, cover transition faults at the gate level quite well. This statement forms the basis for the analysis and comparison of different methods of design for testability (DFT) using software prototype model of the circuit and to select the most appropriate one before the structural synthesis of the circuit. Along with known DFT methods (enhanced scan, launch-on-shift scan and launch-on-capture scan), the authors introduce the method, which is based on the addition of new connections to the circuit in the non-scan testing mode. In order to assess the DFT methods, the functional test is generated for the analysed circuit and the functional delay-fault coverage for this test is evaluated. Each of the considered DFT methods has its own advantages and disadvantages, since they have different delay fault coverage, and require different hardware for their implementation. These differences depend on the function of circuit. The experimental results are provided for the ITC'99 benchmark circuits. The obtained results proved the applicability of the proposed method.
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      Design and evaluation of a high throughput robust router for network-on-chip
      • Author(s): A. Alhussien ; C. Wang ; N. Bagherzadeh
      • Source: IET Computers & Digital Techniques, Volume 6, Issue 3, p. 173 –179
      • DOI:  10.1049/iet-cdt.2011.0082
      • Type: Article
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      • p. 173 –179 (7)
        Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. The faults affect the performance and functionality of the NoC systems and result in communication malfunctions. In this study, a fault tolerant router design with an adaptive routing algorithm that tolerates faults in the network links and the router components is proposed. The approach does not require the use of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed architecture can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.
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      Fast inversion algorithm in GF(2m) suitable for implementation with a polynomial multiply instruction on GF(2)
      • Author(s): K. Kobayashi ; N. Takagi ; K. Takagi
      • Source: IET Computers & Digital Techniques, Volume 6, Issue 3, p. 180 –185
      • DOI:  10.1049/iet-cdt.2010.0006
      • Type: Article
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      • p. 180 –185 (6)
        The authors propose a fast inversion algorithm in Galois field GF(2m). In this algorithm, the operations required in several contiguous iterations of a previously reported algorithm based on the extended Euclid's algorithm are represented as a matrix. These operations are performed at once through the matrix by means of a polynomial multiply instruction on GF(2). When the word size of a processor is 32 or 64 and m is larger than 233 for National Institute of Standards and Technology (NIST)-recommended irreducible polynomials, the proposed algorithm computes inversion with less polynomial multiply instructions on GF(2) and exclusive-OR instructions required by previously reported inversion algorithms on an average.
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      Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow
      • Author(s): Y.-H. Chen ; C.-L. Chang ; C.H.-P. Wen
      • Source: IET Computers & Digital Techniques, Volume 6, Issue 3, p. 186 –193
      • DOI:  10.1049/iet-cdt.2011.0121
      • Type: Article
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      • p. 186 –193 (8)
        As an open defect occurs in one wire segment of the circuit, different logic values on the coupling wires of the physical layout may result in different faulty behaviours, which are so called the Byzantine effect. Many previous researches focus on the test and diagnosis of open defects but the pattern diagnosability has not properly addressed. Therefore in this study, a high-resolution diagnostic framework for open defects is proposed and consists of a diagnostic test-pattern generation (DTPG) and its diagnosis flow. The branch-and-bound search associated with controllability analysis is incorporated in satisfiability-based DTPG to generate patterns for the target segment. Later, a precise diagnosis flow constructs the list of defect candidates in a dictionary-based fashion followed by an inject-and-evaluate analysis to greatly reduce the number of candidates for silicon inspection. Experimental results show that the proposed framework runs efficiently and deduces nearly one candidate for each open-segment defect on average among all ISCAS’85 benchmark circuits.
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