Online ISSN
1751-861X
Print ISSN
1751-8601
IET Computers & Digital Techniques
Volume 6, Issue 1, January 2012
Volumes & issues:
Volume 6, Issue 1
January 2012
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- Author(s): M. Hosseinabady and J.L. Nunez-Yanez
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 1 –11
- DOI: 10.1049/iet-cdt.2010.0097
- Type: Article
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Dynamically reconfigurable platforms based on network-on-chips (NoC) could be a viable option for the deployment of large heterogeneous multicore designs. The dynamic nature of these platforms will mean that run-time application mapping and core management will represent a key challenge since the exact tasks requirements and workloads will not be known a priori. Considering the Manhattan distance among tasks as a measure of efficiency for a mapped application, this study proposes a distributed stochastic dynamic task mapping strategy for mapping applications efficiently onto a large dynamically reconfigurable NoC. The effectiveness of the mapping scheme is investigated considering the transient and steady states of the dynamic platform. The comparison with state-of-the-art centralised dynamic task mapping methods shows more than 26.4% improvement in application communication distance during steady state, which implies lower energy consumption and lower execution time. - Author(s): I. Pomeranz
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 12 –18
- DOI: 10.1049/iet-cdt.2010.0173
- Type: Article
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The use of diagnostic test sets improves the accuracy of defect diagnosis by allowing smaller sets of candidate defect sites to be obtained. However, diagnostic test sets are significantly larger than fault detection test sets, and the complexity of deterministic diagnostic test generation is higher because of the need to consider pairs of faults. This work studies a solution that addresses both the size of a diagnostic test set and the complexity of deterministic diagnostic test generation through the use of what are called test vector chains. Test vector chains provide a specific algorithm for obtaining new tests from existing ones through single-bit changes. They allow smaller test sets to be stored, and additional tests to be obtained by computing test vector chains or subsets thereof. Experimental results demonstrate that tests obtained through test vector chains are effective as diagnostic tests, and that the resulting storage requirements are close to those of fault detection test sets. - Author(s): S. Mitra ; P. Ghosh ; P. Dasgupta
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 19 –32
- DOI: 10.1049/iet-cdt.2010.0048
- Type: Article
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This study explores the utility of reusing proven component invariants in the backward reachability-based sequential equivalence checking paradigm of formal verification. The authors present a formal method for simplifying the process of proving global invariants on an integrated design using the reachability information of the component state spaces, obtained from known invariants for the components of the design. Experimental results on benchmark circuits reveal that deriving the approximate reachability don't cares from the proofs of component invariants helps in reducing both the depth and breadth of the search. - Author(s): F. Xia ; A. Mokhov ; Y. Zhou ; Y. Chen ; I. Mitrani ; D. Shang ; D. Sokolov ; A. Yakovlev
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 33 –42
- DOI: 10.1049/iet-cdt.2010.0091
- Type: Article
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This study describes power-elastic systems, a method for designing systems whose operations are limited by applicable power. Departing from the traditional low-power design approach which minimises the power consumption for given amounts of computation throughput, power-elastic design focuses on the maximally effective use of applicable power. Centred on a run-time feedback control architecture, power-elastic systems manage their computation loads according to applicable power constraints, effectively viewing quantities of power as resources to be distributed among units of computation. Concurrency management is demonstrated as an effective means of implementing such run-time control, through both theoretical and numerical investigations. Several concurrency management techniques are studied and the effectiveness of arbitration for dynamic concurrency management with minimal prior system knowledge is demonstrated. A new type of arbitration, called soft arbitration, particularly suitable for managing the access of flexible resources such as power, is developed and proved. - Author(s): T. Nakabayashi ; T. Sasaki ; K. Ohno ; T. Kondo
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 43 –49
- DOI: 10.1049/iet-cdt.2011.0027
- Type: Article
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Enhancement of mobile computers requires high-performance computing with low-energy consumption. Variable stages pipeline (VSP) architecture, which reduces energy consumption and improves execution time by dynamically unifying the pipeline stages, is proposed to achieve this requirement. A VSP processor uses a special pipeline register called a latch D-flip-flop selector-cell (LDS-cell) that unifies the pipeline stages and prevents glitch propagation caused by stage unification under low-energy mode. The design of the fabricated VLSI of a VSP processor chip on 0.18 µm CMOS technology is presented. An evaluation shows that the VSP processor consumes 13% less energy than a conventional one. - Author(s): S. Wang ; J. Hu ; S.G. Ziavras
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 50 –58
- DOI: 10.1049/iet-cdt.2010.0102
- Type: Article
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Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar and simultaneous multi-threading (SMT) processors for instruction-level parallelism and thread-level parallelism exploitation. However, the large BTB not only dominates the predictor energy consumption, but also becomes a major roadblock in achieving faster clock frequencies at deep sub-micron technologies. The authors propose here a filtering scheme to dramatically reduce the accesses to the BTB to achieve significantly reduced energy consumption in the BTB while maintaining the performance. For a simulated superscalar microprocessor, the experimental evaluation shows that the BTB access filtering (BAF) design achieves an 88.5% dynamic energy reduction with negligible performance loss. The authors also study the leakage behaviour and its control in the BAF design. The results show that by applying a drowsy strategy, very effective leakage control can be achieved. For the high-performance design, the BAF can also improve BTB's performance scalability at new technologies. For the simultaneous multi-threading environment, the authors evaluate the effectiveness of the BAF design and propose a banked BAF (BK-BAF) scheme to further reduce the energy consumption and performance overhead. The experimental results confirm that the BK-BAF scheme can be an energy/performance-effective design for next generation SMT processors. - Author(s): J.Y. Hur ; T. Stefanov ; S. Wong ; K. Goossens
- Source: IET Computers & Digital Techniques, Volume 6, Issue 1, p. 59 –68
- DOI: 10.1049/iet-cdt.2010.0105
- Type: Article
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Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in field-programmable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor system combined with the presented custom crossbar has been designed with the ESPAM design environment and prototyped in the FPGA device. Experiments with practical applications show that the custom crossbar occupies significantly less area, maintains higher performance and reduces the power consumption, when compared with the general-purpose crossbars. In addition, the authors present that configuration performance and cost can be improved by reducing the functional area cost in FPGAs. Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping. The presented customised NoC is implemented in FPGA and results indicate that the area is reduced by 66%, when compared with the general-purpose networks.
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles
Test vector chains for increased resolution and reduced storage of diagnostic tests
Verification by parts: reusing component invariant checking results
Towards power-elastic systems through concurrency management
Design and evaluation of variable stages pipeline processor with low-energy techniques
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
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