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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 6, Issue 1, January 2012

Volume 6, Issue 1

January 2012

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    • Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles
      Test vector chains for increased resolution and reduced storage of diagnostic tests
      Verification by parts: reusing component invariant checking results
      Towards power-elastic systems through concurrency management
      Design and evaluation of variable stages pipeline processor with low-energy techniques
      Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures
      Customisation of on-chip network interconnects and experiments in field-programmable gate arrays

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