Online ISSN
1751-861X
Print ISSN
1751-8601
IET Computers & Digital Techniques
Volume 5, Issue 5, September 2011
Volumes & issues:
Volume 5, Issue 5
September 2011
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- Author(s): G. Paci ; D. Bertozzi ; L. Benini
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 355 –365
- DOI: 10.1049/iet-cdt.2009.0103
- Type: Article
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p.
355
–365
(11)
Adaptive body bias (ABB) and adaptive supply voltage (ASV) are effective methods for post-silicon tuning to reduce variability on generic combinational circuits or microprocessor circuit sub-blocks. We focus in this work on global point-to-point interconnects, which are evolving into complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterisation of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the effectiveness of ABB against ASV when put at work on two on-chip point-to-point link architectures: a traditional full-swing and a low-swing signalling scheme for low-power communication. This work provides guidelines for the post-silicon variability compensation of these communication channels, while considering realistic layout effects. In particular, the implications of cross-coupling capacitance on the effectiveness of variability compensation are analysed in this work. - Author(s): F. Plessas ; A. Alexandropoulos ; S. Koutsomitsos ; E. Davrazos ; M. Birbas
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 366 –374
- DOI: 10.1049/iet-cdt.2010.0143
- Type: Article
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p.
366
–374
(9)
Advanced and dynamic calibration techniques for maximising the link performance of parallel source–synchronous interfaces are introduced and demonstrated in this study, using as a case study a 533 MHz DDR2 SDRAM memory interface implemented in 90 nm standard complementary metal-oxide-semiconductor (CMOS), whereas most of them have been validated at 800 MHz too. A novel dynamic strobe masking system (DSMS) has also been employed which, in contrast to traditional techniques, adjusts dynamically the length of the masking signal in real time, based on the incoming strobe. Furthermore, optimal data capture is achieved by employing a fast bit-deskew calibration engine, while also a novel I/O calibration scheme is included. Post-layout simulation results demonstrate that the dynamic calibration and skew compensation techniques employed improve the timing margin while providing advanced robustness over process, voltage and temperature variations. - Author(s): H. Shao ; X. Li ; C-Y. Tsui
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 375 –385
- DOI: 10.1049/iet-cdt.2009.0065
- Type: Article
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p.
375
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(11)
Robustness is the main concern in the design of level converters (LCs) for sub-threshold voltage applications. Besides this, when a sub-threshold voltage is applied to the input of the LC, the output transition time of the LC is very long and the short-circuit current through the logic gates that are driven by the LC output is large. The circuit's total energy consumption increases. In this study, a novel single-stage LC that can operate robustly for sub-threshold signal is firstly presented. Based on the single-stage LC circuit, a multi-stage sub-threshold LC structure is proposed, which features similar operation robustness, and at the same time, greatly reduces the output transition time of the LC. As a result, the circuit's total energy consumption (including that of the fanout logic gates) is significantly reduced. Extensive simulations were carried out to demonstrate the operation robustness of the authors proposed multi-stage sub-threshold LC. Measurements were done on a fabricated test chip to verify the operation and demonstrate the performance improvement of the design. - Author(s): N. Chabini and M.C. Wolf
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 386 –392
- DOI: 10.1049/iet-cdt.2010.0024
- Type: Article
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Execution time is no longer the only target to achieve when designing programmes for today and next-generation CMOS-based digital systems. One needs to also consider reducing power dissipation. Buses contribute to the power dissipation during the execution of a given programme since instructions and/or operands have to be fetched from the memory. Reducing power dissipation in buses has been addressed in the literature. In this study, the authors address the problem of reducing power dissipation of the instruction bus by reordering the instructions in basic blocks without increasing the executing time and the code size, and while maintaining the original functionality of the programme. The authors target embedded processors having Harvard architecture. They focus on solving this problem for programmes developed at the assembly level, since at that level the machine code can be obtained by simply running an assembler, which allows an accurate computation of switching activities on the instruction bus by considering each pair of instructions. The authors formulate this problem as an integer linear programme (ILP), and they provide two heuristics. Experimental results have shown that the proposed approach can reduce switching activities. The ILP has reduced switching activities by as high as 38%. One of the two proposed heuristics has always resulted in reducing switching activities, and its relative savings are within an average of 5% from the optimum produced using the ILP. - Author(s): A. Kaivani ; A. Hosseiny ; G. Jaberipur
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 393 –404
- DOI: 10.1049/iet-cdt.2010.0026
- Type: Article
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The authors study previous major contributions to digit recurrence decimal division hardware and focus on techniques for improving the performance of quotient digit selection (QDS) as the most complex part. In particular, Design D1 uses the digit set [−5, 5] for quotient digits. Another design (D2) uses mixed binary/decimal carry-save manipulation of the few most significant digits of partial remainders. Motivated by successful combined arithmetic algorithms such as hybrid adders, the authors offer a decimal division scheme that takes advantage of the best design options of D1 and D2 with due modifications that significantly enhance the division speed. In particular, they configure the architectures of QDS and partial remainder computation paths in favour of reduced balanced latencies of both. Furthermore, they remove the rounding cycle by cost-free auto-rounding, which is an exclusive advantage of the digit set [−5, 5]. The authors of D1 and D2 have used logical effort (LE) and circuit synthesis to evaluate their dividers, respectively. Therefore for a fair comparison, the authors evaluate the proposed design (D3) with both methods. The LE-based D3/D1 comparison shows 21% more speed at the cost of 6% more area, whereas the synthesis-based D3/D2 comparison results in 46% less latency and 23% less area. - Author(s): I. Pomeranz and S.M. Reddy
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 405 –414
- DOI: 10.1049/iet-cdt.2010.0049
- Type: Article
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The trade-off between strong and weak non-robust tests for path delay faults considering test quality, test set size and fault coverage is discussed. It is noted that strong non-robust tests detect more combinations of delay defects. However, weak non-robust tests result in smaller test sets, and more path delay faults are detectable by weak non-robust tests. A test generation strategy that mixes strong and weak non-robust tests based on this trade-off is described. Under the proposed strategy, test generation starts by generating strong non-robust tests. When the number of faults detected by each additional test drops below a certain level, indicating that low levels of compaction are achieved, test generation switches to weak non-robust tests. The authors study appropriate switching points experimentally by using a test selection procedure to construct mixed test sets. They also consider the effects of adding power constraints on the mix of strong and weak non-robust tests. - Author(s): I. Pomeranz and S.M. Reddy
- Source: IET Computers & Digital Techniques, Volume 5, Issue 5, p. 415 –423
- DOI: 10.1049/iet-cdt.2010.0014
- Type: Article
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p.
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The authors define the notion of a lingering synchronisation effect. Such an effect occurs when a primary input cube (an incompletely specified primary input vector) determines the state of a circuit for several time units after it is applied. A primary input cube with a lingering synchronisation effect may prevent certain faults from being detected when it appears repeatedly in a test sequence. It should therefore be avoided when the goal is to achieve a high fault coverage. The authors demonstrate that benchmark circuits have primary input cubes with small numbers of specified values (typically one or two), which have lingering synchronisation effects. In some cases, the synchronisation effects linger for large numbers of time units. The authors define a ranking of primary input cubes based on the severity of their lingering synchronisation effects. They describe a random test generation process that avoids primary input cubes with lingering synchronisation effects, and achieves high fault coverage for benchmark circuits. The test generation process uses the severity of the lingering synchronisation effects of the primary input cubes to decide on the ones it should avoid.
Variability compensation for full-swing against low-swing on-chip communication
Advanced calibration techniques for high-speed source–synchronous interfaces
Low energy multi-stage level converter for sub-threshold logic
Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus
Improving the speed of decimal division
Sizes of test sets for path delay faults using strong and weak non-robust tests
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation
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