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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 5, Issue 4, July 2011

Volume 5, Issue 4

July 2011

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    • Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computation
      Field programmable gate array-based acceleration of shortest-path computation
      Row-linear feedback shift register-column X-masking technique for simultaneous testing of many-core system chips
      Two-dimensional partially functional broadside tests
      History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors
      Fault model and test procedure for phase change memory
      Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array
      Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table
      State assignment for sequential circuits using multi-objective genetic algorithm
      Novel hazard-free majority voter for N-modular redundancy-based fault tolerance in asynchronous circuits

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