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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 5, Issue 3, May 2011

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Volume 5, Issue 3

May 2011

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  • Three-dimensional integrated circuits design

    • Editorial: Three-dimensional integrated circuits design
      Integration schemes and enabling technologies for three-dimensional integrated circuits
      • Author(s): K.N. Chen  and  C.S. Tan
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 160 –168
      • DOI:  10.1049/iet-cdt.2009.0127
      • Type: Article
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      • p. 160 –168 (9)
        Various integration schemes and key enabling technologies for wafer-level three-dimensional integrated circuits (3D IC) are reviewed and discussed. Stacking orientations (face up or face down), methods of wafer bonding (metallic, dielectric or hybrid), formation of through-silicon via (TSV) (via first, via middle or via last) and singulation level (wafer-to-wafer or chip-to-wafer) are options for 3D IC integration schemes. Key enabling technologies, such as alignment, Cu–Cu bonding and TSV fabrication, are described as well. Improved performance, such as lower latency and higher bandwidth, lower power consumption, smaller form factor, lower cost and heterogeneous integration of disparate functionalities, are made possible in the next generation of electronics products with the realisation of 3D IC.
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      Thermal–electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints
      • Author(s): A. Jain ; S.M. Alam ; S. Pozder ; R.E. Jones
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 169 –178
      • DOI:  10.1049/iet-cdt.2009.0107
      • Type: Article
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      • p. 169 –178 (10)
        Although the stacking of multiple strata to produce three-dimensional (3D) integrated circuits (ICs) improves interconnect length and hence reduces power and latency, it also results in the exacerbation of the thermal management challenge owing to the increased power density. There is a need for design tools to understand and optimise the trade-off between electrical and thermal design at the device and block levels. This study presents results from thermal–electrical co-optimisation for block-level floorplanning in a multi-die 3D IC under various manufacturing and physical design constraints. A method for temperature computation based on linearity of the governing energy equation is presented. This method is combined with previously reported electrical delay models for 3D ICs to simultaneously optimise both the maximum temperature and the interconnect length. It is shown that co-optimisation of thermal and electrical objectives results in a floorplan that is attractive from both perspectives. Physical design constraints because of cost-effective 3D manufacturing such as using fully or partly identical dies using reciprocal design symmetry (RDS), differentiated technology in each die and thinned die/wafer are discussed and their impact on the thermal–electrical co-optimisation is investigated. In some cases, the cheapest manufacturing choice, such as using identical die, for each layer may not result in optimal thermal and electrical design. Results presented in this work highlight the need for thermal and electrical co-design in multi-strata microelectronics, and for reconciling manufacturing and design considerations in order to develop practical design tools for 3D ICs.
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      Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse
      • Author(s): C.-M. Hung  and  Y.-L. Lin
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 179 –185
      • DOI:  10.1049/iet-cdt.2009.0118
      • Type: Article
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      • p. 179 –185 (7)
        The authors propose a platform-based approach called Chipsburger for three-dimensional integrated circuits (3D IC) implementation of multiple electronics systems. The authors emphasise manufacturing reuse to lower the total non-recurring engineering and mass-production cost of 3D chips for multiple applications. Given a set of applications each employing a set of IPs and needing a certain amount of mass-production volume, the author's target 3D IC stack consists of platform dies and customised dies. Platform dies can be manufactured in large volume at low unit cost and used in multiple applications; Customised dies for individual application, on the other hand, will be smaller and easier to implement, as certain functionality has been allocated to the platform dies. The authors have developed a 3D IC cost model to evaluate platform-die configurations and compare the cost benefit of Chipsburger with that of either one 2D system-on-a-chip or 3D IC per application. The authors also develop a platform generator program for finding an optimised platform for a set of applications. Experimental results over industrial examples indicate that Chipsburger is indeed cost-effective for certain range of volume requirements.
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      Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips
      • Author(s): B. Noia  and  K. Chakrabarty
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 186 –197
      • DOI:  10.1049/iet-cdt.2009.0111
      • Type: Article
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      • p. 186 –197 (12)
        System-on-chip (SOC) designs comprised of a number of embedded cores are widespread in today's integrated circuits. Embedded core-based design is likely to be equally popular for three-dimensional integrated circuits (3D ICs), the manufacture of which has become feasible in recent years. 3D integration offers a number of advantages over traditional 2D technologies, such as the reduction in the average interconnect length, higher performance, lower interconnect power consumption and smaller IC footprint. Despite recent advances in 3D fabrication and design methods, no attempt has been made thus far to design a 1500-style test wrapper for an embedded core that spans multiple layers in a 3D SOC. This study addresses wrapper optimisation in 3D ICs based on through-silicon vias (TSVs) for vertical interconnects. The authors objective is to minimise the scan-test time for a core under constraints on the total number of TSVs available for testing. The authors present an optimal solution based on an integer linear programming model as well as two polynomial-time heuristic solutions. Simulation results are presented for embedded cores from the ITC 2002 SOC test benchmarks.
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      Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor
      • Author(s): T. Thorolfsson ; N. Moezzi-Madani ; P.D. Franzon
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 198 –204
      • DOI:  10.1049/iet-cdt.2009.0106
      • Type: Article
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      • p. 198 –204 (7)
        In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70% when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5% and the footprint by 49.2%, and allows the PE to operate 7.1% faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70%. Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.
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      Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration
      • Author(s): T. Karnik ; D. Somasekhar ; S. Borkar
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 205 –212
      • DOI:  10.1049/iet-cdt.2009.0126
      • Type: Article
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      • p. 205 –212 (8)
        Promise of form-factor reduction and hybrid process integration by three-dimensional (3D)-stacked integrated circuits (3DICs) has spurred interest in both academia and industry. In this study, through-silicon-via (TSV)-based 3D integration is discussed from a microprocessor centric view. The authors present the challenges faced by technology scaling and provide 3D integration as a possible solution. The applications for 3DICs are discussed with details of a few prototypes. The issues and challenges associated with 3D integration technologies are also addressed. TSV-based 3D integration technology will allow integration of diverse functionality to realise energy-efficient and affordable compact systems that will continue to deliver higher performance.
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      Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation
      • Author(s): X. Dong ; X. Wu ; Y. Xie ; Y. Chen ; H. Li
      • Source: IET Computers & Digital Techniques, Volume 5, Issue 3, p. 213 –220
      • DOI:  10.1049/iet-cdt.2009.0091
      • Type: Article
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      • p. 213 –220 (8)
        Magnetic random access memory (MRAM) has been considered as a promising memory technology because of its attractive properties such as non-volatility, fast access, zero standby leakage and high density. Although integrating MRAM with complementary metal-oxide-semiconductor (CMOS) logic may incur extra manufacturing cost because of the hybrid magnetic-CMOS fabrication process, it is feasible and cost-effective to fabricate MRAM and CMOS logic separately and then integrate them using 3D stacking. In this work, we first studied the MRAM properties and built an MRAM cache model in terms of performance, energy and area. Using this model, we evaluated the impact of stacking MRAM caches atop microprocessor cores and compared MRAM against its static random access memory (SRAM) and dynamic random access memory (DRAM) counterparts. Our simulation result shows that MRAM stacking can provide competitive instruction-per-cycle (IPC) performance with a large reduction in power consumption.
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