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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 4, Issue 5, September 2010

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Volume 4, Issue 5

September 2010

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    • Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding
      • Author(s): L. Lu ; J.V. McCanny ; S. Sezer
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 349 –364
      • DOI:  10.1049/iet-cdt.2008.0106
      • Type: Article
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      • p. 349 –364 (16)
        A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.
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      Static test compaction for diagnostic test sets of full-scan circuits
      • Author(s): I. Pomeranz  and  S.M. Reddy
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 365 –373
      • DOI:  10.1049/iet-cdt.2009.0110
      • Type: Article
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      • p. 365 –373 (9)
        The authors describe a static test compaction procedure for diagnostic test sets of full-scan circuits. Similar to reverse order and random order fault simulation procedures applied to fault detection test sets, the procedure simulates the test set in different orders in order to identify unnecessary tests. Two features distinguish the procedure from earlier ones. (i) It uses a diagnostic fault simulation process based on equivalence classes to identify tests that are not necessary for distinguishing fault pairs. (ii) It includes an iterative reordering process whose goal is to increase the number of tests that will be identified as unnecessary. Experimental results are presented to demonstrate the ability of the procedure to compact diagnostic test sets and the effectiveness of the iterative reordering process.
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      Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains
      • Author(s): M. Lai ; L. Gao ; Z. Wang
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 374 –387
      • DOI:  10.1049/iet-cdt.2009.0041
      • Type: Article
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      • p. 374 –387 (14)
        The exploration and design process of highly efficient processor element for multimedia and signal processing domains is presented in this study. With the introduction of synchronous data-transfer architecture for high-performance embedded applications, the effectively exploring the exponential-size architectural design spaces by detailed simulation is intractable. The authors attack this via an automated approach. At first, its cost model is built to achieve fast and accurate estimation with the characteristic of scalability. Then, the hierarchical design space exploration methodology involving heuristic-based local process and analytical global optimisation step is proposed to achieve the approximate optimum with short time-to-market. For target domains, our proposed method arrives at better optimised results within only 25 h when compared with other methods. A System on Chip (SoC) involving the optimised processor element has been implemented in 0.13 µm complementary metal oxide semiconductor (CMOS) process and the experimental results show that our processor element outperforms TMS320C64 series and does the obvious acceleration to multimedia applications in SoC system.
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      Robust intellectual property protection of VLSI physical design
      • Author(s): D. Saha  and  S. Sur-Kolay
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 388 –399
      • DOI:  10.1049/iet-cdt.2008.0152
      • Type: Article
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      • p. 388 –399 (12)
        In deep sub-micron VLSI, increased demand for design productivity of ICs with millions of devices has led to widespread design reuse. This however enhances the probability of infringement of intellectual property (IP) of the design. Typically, repudiation attack by the IP owner through challenging the legality of the buyer and additive attack through insertion of additional marks in the design are not considered in the design cycle. Moreover, public watermark verification is still not secure, as attacker manages to override the mark with his own one. Our proposed algorithm ROBUST_IP tackles these issues with a modified IP marking schema. Firstly, it introduces a master key of an independent intellectual property protection (IPP) team to eliminate the scope of repudiation attack, renders insertion of fake marks useless and can efficiently extract the signatures of legal IP owner and buyer in absence of any claim. Secondly, the concept of a new parameter, public_verification_count, enhances security during public mark verification. Finally, novel techniques based on this schema are proposed to embed marks in the physical design phase specifically for ASIC and FPGA design. Experimental results on MCNC benchmarks demonstrate that removal/tampering of marks remain infeasible at the cost of insignificant overhead in area/delay.
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      System-level power management for system-on-a-chip -based mobile devices
      • Author(s): J. Choi  and  H. Cha
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 400 –409
      • DOI:  10.1049/iet-cdt.2008.0074
      • Type: Article
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      • p. 400 –409 (10)
        Since power management policies tend to have limits when based on individual components of a system, such as the processor, memory or LCD, it is necessary to have a system-wide approach that considers power components in an integrated way. The system-on-a-chip (SoC) that has been commonly adopted in handheld devices is one system in particular that requires the close interactions among the components; hence, power management policy should be developed appropriately. In this study, the authors propose a system-level power management approach that considers dynamic voltage and frequency scaling (DVFS) of the processor core in relation to other power consumers. The authors show that the proposed policy reduces the power consumption of a mobile device by 25–42%, depending on the application.
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      Low-power dual-edge triggered state-retention scan flip-flop
      • Author(s): H. Karimiyan ; S.M. Sayedi ; H. Saidi
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 410 –419
      • DOI:  10.1049/iet-cdt.2009.0059
      • Type: Article
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      • p. 410 –419 (10)
        This study presents a dual-edge triggered static scanable flip-flop suitable for low-power applications. The proposed circuit deploys reduced swing-clock and swing-data to manage dynamic power. Furthermore, it employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The static structure of the circuit makes it feasible to be used in variable frequency power control designs. HSPICE post-layout simulation conducted for 90 nm complementary metal-oxide semiconductor technology indicates that in addition to state retention and test capability, the proposed design, in terms of power-delay product, device count and leakage power is comparable to other high-performance flip-flops.
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      Low-overhead single-event upset hardened latch using programmable resistance cells
      • Author(s): X. She  and  N. Li
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 420 –427
      • DOI:  10.1049/iet-cdt.2009.0026
      • Type: Article
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      • p. 420 –427 (8)
        This study presents a single-event upset (SEU) hardened latch having first and second cross-coupled inverters and first and second programmable resistance metallisation cells. The metallisation cells may be programmed to low or high-resistance states. When set to a low-resistance state, the latch may be accessed to write a new logic state into the latch. When reset to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from getting affected by SEUs. This technique introduces little layout penalty, does not adversely affect circuit speed and is simple to implement in conventional semiconductor manufacturing process flow.
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      Simplified bit parallel systolic multipliers for special class of Galois field (2m) with testability
      • Author(s): H. Rahaman ; J. Mathew ; A.M. Jabir ; D.K. Pradhan
      • Source: IET Computers & Digital Techniques, Volume 4, Issue 5, p. 428 –437
      • DOI:  10.1049/iet-cdt.2009.0068
      • Type: Article
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      • p. 428 –437 (10)
        This study presents a simplified structure of bit parallel systolic multiplier over Galois fields (GFs) over the set GF(2m) suitable for cryptographic hardware implementation. A redundant standard basis representation with the irreducible all one polynomial is considered. The systolic multiplier consists of (m+1)2 identical cells, each consisting of one two-input AND gate, one two-input XOR gate and two one-bit latches. This architecture is well suited to very large-scale integration implementation because of its regularity modular structure and unidirectional data flow. The proposed multipliers have clock cycle latency of (m+1). This architecture has a total reduction of m2 D-flip-flops compared to earlier bit parallel systolic multiplication architecture. As the finite-field multiplier is one of the complex blocks in cryptographic hardware and need secure testability to avoid unwanted access into the on-chip security blocks, the authors also introduce an on-chip testing scheme. The authors propose a test generation technique for detecting stuck-at fault (SAF), transition delay fault (TDF), stuck-open fault (SOF) and path delay faults (PDFs) at the gate and cell level in the systolic architecture. The authors also show that realistic sequential cell fault can be detected only by 12 single input change test vectors in the complete systolic multiplier over GF(2m). The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of an automatic test pattern generation tool. The complete systolic architecture is C-testable for SAF, TDF, SOF and PDF with only 12 constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF, TDF, SOF and PDF coverage.
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