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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 3, Issue 3, May 2009

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Volume 3, Issue 3

May 2009

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    • Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems
      • Author(s): Q. Liu ; G.A. Constantinides ; K. Masselos ; P.Y.K. Cheung
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 235 –246
      • DOI:  10.1049/iet-cdt.2008.0039
      • Type: Article
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      • p. 235 –246 (12)
        Contemporary FPGA-based reconfigurable systems have been widely used to implement data-dominated applications. In these applications, data transfer and storage consume a large proportion of the system energy. Exploiting data-reuse can introduce significant power savings, but also introduces the extra requirement for on-chip memory. To aid data-reuse design exploration early during the design cycle, the authors present an optimisation approach to achieve a power-optimal design satisfying an on-chip memory constraint in a targeted FPGA-based platform. The data-reuse exploration problem is mathematically formulated and shown to be equivalent to the multiple-choice knapsack problem. The solution to this problem for an application code corresponds to the decision of which array references are to be buffered on-chip and where loading reused data of the array references into on-chip memory happen in the code, in order to minimise power consumption for a fixed on-chip memory size. The authors also present an experimentally verified power model, capable of providing the relative power information between different data-reuse design options of an application, resulting in a fast and efficient design-space exploration. The experimental results demonstrate that the approach enables us to find the most power-efficient design for all the benchmark circuits tested.
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      Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems
      • Author(s): J.E. Rice  and  K.B. Kent
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 247 –258
      • DOI:  10.1049/iet-cdt.2008.0042
      • Type: Article
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      • p. 247 –258 (12)
        Reconfigurable hardware has recently shown itself to be an appropriate solution to speeding up problems that are highly dependent on a particular complex or repetitive sub-algorithm. In most cases, these types of solutions lend themselves well to parallel solutions. The optimal design on field programmable gate arrays (FPGAs) for problems with algorithms or sub-algorithms that can be highly parallelised is investigated. In addition, a classification system is introduced, which categorises FPGA-based solutions into ‘instance-specific’ and ‘parameter-specific’.
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      Intellectual property core implementation of decision trees
      • Author(s): R.J.R. Struharik  and  L.A. Novak
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 259 –269
      • DOI:  10.1049/iet-cdt.2008.0055
      • Type: Article
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      • p. 259 –269 (11)
        Several soft intellectual property (IP) core implementations of decision trees (axis-parallel, oblique and nonlinear) based on the concept of universal node (UN) and sequence of UNs are presented. Proposed IP cores are suitable for implementation in both field programmable gate arrays and application specific integrated circuits. Developed IP cores can be easily customised in order to fit a wide variety of application requirements, fulfilling their role as general purpose building blocks for SoC designs. Experimental results obtained on 23 data sets of standard UCI machine learning repository database suggest that the proposed architecture based on the sequence of UNs requires on average 56% less hardware resources compared with previously proposed architectures, having the same throughput.
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      Efficient advanced encryption standard implementation using lookup and normal basis
      • Author(s): F. Burns ; J. Murphy ; A. Koelmans ; A. Yakovlev
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 270 –280
      • DOI:  10.1049/iet-cdt.2008.0049
      • Type: Article
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      • p. 270 –280 (11)
        A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.
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      Single error correctable bit parallel multipliers over GF(2m)
      • Author(s): J. Mathew ; A.M. Jabir ; H. Rahaman ; D.K. Pradhan
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 281 –288
      • DOI:  10.1049/iet-cdt.2008.0015
      • Type: Article
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      • p. 281 –288 (8)
        Motivated by the problems associated with soft errors in digital circuits and fault-related attacks in cryptographic hardware, a systematic method for designing single error correcting multiplier circuits is presented for finite fields or Galois fields over GF(2m). Multiple parity predictions to correct single errors based on the Hamming principles are used. The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. This technique, when compared with existing ones, gives better performance. It is shown that single error correction (SEC) multipliers over GF(2m) require slightly over 100% extra hardware, whereas with the traditional SEC techniques, this figure is more than 200%. Since single bit internal faults can cause multiple faults in the outputs, this has also been addressed here by using multiple Hamming codes with optimised hardware.
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      Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
      • Author(s): M. Fazeli ; S.G. Miremadi ; A. Ejlali ; A. Patooghy
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 289 –303
      • DOI:  10.1049/iet-cdt.2008.0099
      • Type: Article
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      • p. 289 –303 (15)
        Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.
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      Time-space test response compaction and diagnosis based on BCH codes
      • Author(s): F.-M. Wang ; W.-C. Wang ; J.C.-M. Li
      • Source: IET Computers & Digital Techniques, Volume 3, Issue 3, p. 304 –313
      • DOI:  10.1049/iet-cdt.2008.0066
      • Type: Article
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      • p. 304 –313 (10)
        A test response compaction and diagnosis technique based on BCH error correction code is presented. Traditional time-domain BCH compaction is not very useful in practice because the area overhead is too large. On the other hand, space-domain BCH compaction does not have a sufficient compression ratio to support a multiple error diagnosis. The proposed time-space compaction technique shares the polynomials among scan chains to reduce the area overhead A Boolean satisfiability optimiser is employed to diagnose the minimum number of errors. In addition, an analytical model is proposed to estimate the aliasing probability, which helps to determine key parameters of the proposed compactor. To diagnose ten errors in a design of 500 k flip-flops, the compression ratio is more than 2600 and the area overhead is <5% of flip-flops.
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