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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 3, Issue 3, May 2009

Volume 3, Issue 3

May 2009

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    • Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems
      Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems
      Intellectual property core implementation of decision trees
      Efficient advanced encryption standard implementation using lookup and normal basis
      Single error correctable bit parallel multipliers over GF(2m)
      Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
      Time-space test response compaction and diagnosis based on BCH codes

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