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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 3, Issue 2, March 2009


Volume 3, Issue 2

March 2009

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    • Reconfigurable broadcast scan compression using relaxation-based test vector decomposition
      Interconnect and communication synthesis for distributed register-file microarchitecture
      Droop sensitivity of stuck-at fault tests
      Design networks-on-chip with latency/bandwidth guarantees
      Utilisation of inverse compatibility for test cost reductions
      High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms
      Test vector chains for increasing the fault coverage and numbers of detections

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