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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 2, Issue 5, September 2008

Volume 2, Issue 5

September 2008

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    • Efficient test compression technique based on block merging
      Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array
      Exploring architectural solutions for energy optimisations in bus-based system-on-chip
      Energy efficient i-cache using multiple line buffers with prediction
      Model order reduction by Miller's theorem and root localisation
      Control-theoretic dynamic voltage scaling for embedded controllers
      Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

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