Online ISSN
1751-861X
Print ISSN
1751-8601
IET Computers & Digital Techniques
Volume 2, Issue 3, May 2008
Volumes & issues:
Volume 2, Issue 3
May 2008
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- Author(s): A.H. El-Maleh
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 155 –163
- DOI: 10.1049/iet-cdt:20070028
- Type: Article
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p.
155
–163
(9)
One of the major challenges in testing a system-on-a-chip is dealing with the large volume of test data. To reduce the volume of test data, several test data compression techniques have been proposed. Frequency-directed run-length (FDR) code is a variable-to-variable run length code based on encoding runs of 0s. It is demonstrated that higher test data compression can be achieved based on encoding both runs of 0s and 1s. An extension to the FDR code is proposed and by experimental results its effectiveness in achieving a higher compression ratio is demonstrated. - Author(s): B. Matthews and I. Elhanany
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 164 –171
- DOI: 10.1049/iet-cdt:20070027
- Type: Article
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p.
164
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(8)
A novel hardware architecture for performing the core computations required by dynamic programming (DP) techniques is introduced. The latter pertain to a vast range of applications that necessitate an optimal sequence of decisions to be obtained. An underlying assumption is that a complete model of the environment is provided, whereby the dynamics are governed by a Markov decision process. Existing DP implementations have traditionally focused on software-based mechanisms. Here, the authors present a method for exploiting the inherent parallelism associated with computing both the value function and optimal policy. This allows for the optimal policy to be obtained several orders of magnitude faster than traditional software implementations, establishing the viability of the approach for demanding, real-time applications. The well-known rental car management problem has been studied as a benchmark for which a field-programmable gate array-based implementation was designed. The results highlight the advantages of the proposed approach with respect to the execution speed and the scalability properties. - Author(s): X. She
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 172 –183
- DOI: 10.1049/iet-cdt:20070118
- Type: Article
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172
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Many examples of reconfigurable fault-tolerant hardware consist of cells that have the same hardware structure. The arithmetic or logical functions of the cells can be configured. The interconnection of the configured cells can perform a complex task. The interconnection of these cells can be configured too. When some cells are faulty, the function and routing of some cells have to be reconfigured to restore the system's normal function. Most published fault-tolerant schemes cannot automatically achieve fault tolerance without the aid of external software and hardware, or they will require a long routing time to restore normal system function. Some published fault-tolerant schemes require a massive amount of spare cells. A self-routing, reconfigurable and fault-tolerant cell array is presented. When some cells are faulty, spare cells can automatically replace the faulty cells and rerouting can be automatically achieved. The cell array automatically achieves fault tolerance without the aid of external software or hardware, using a small amount of spare cells. In addition, the proposed cell array achieves short routing time to quickly restore normal system function. - Author(s): J.L. Nunez-Yanez ; D. Edwards ; A.M. Coppola
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 184 –198
- DOI: 10.1049/iet-cdt:20060175
- Type: Article
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p.
184
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An investigation into an effective and low-complexity adaptive routing strategy based on stochastic principles for an asynchronous network-on-chip platform that includes dynamically reconfigurable computing nodes is presented. The approach is compared with classic deterministic routing and it is shown to have good properties in terms of throughput and excellent fault-tolerance capabilities. The challenge of how to deliver reliability is one of the problems that multiprocessor system architects and manufactures will face as feature sizes and voltage supplies shrink and deep-submicron effects reduce the ability to carry out deterministic computing. It is likely that a new type of deep-submicron complex multicore systems will emerge which will be required to deliver high performance within strict energy and area budgets and operate over unreliable silicon. Within this context, the paper studies an on-chip communication infrastructure suitable for these systems. - Author(s): F. Rivera ; M. Sanchez-Elez ; R. Hermida ; N. Bagherzadeh
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 199 –213
- DOI: 10.1049/iet-cdt:20070085
- Type: Article
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199
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The authors present a scheduling methodology for conditional execution of kernels onto single instruction stream/multiple data stream multicontext reconfigurable architectures. Data flow graphs are used to describe the target applications in which some kernels are conditionally executed depending on runtime conditions. Immediately after testing a condition the next kernel to be processed is known and its configurations and input data can be loaded, producing a computation stall while these transfers are performed. A compilation-time kernel scheduling is proposed to handle conditional branches (CBs) by determining a kernel sequence that minimises these computation stalls reducing the application latency. Target applications are firstly partitioned taking into account the presence of CBs, and then kernels are ordered for execution and mapped onto the reconfigurable system. Experimental results obtained for interactive and synthetic applications demonstrate the effectiveness of the proposal. - Author(s): K. Gulati ; M. Waghmode ; S.P. Khatri ; W. Shi
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 214 –229
- DOI: 10.1049/iet-cdt:20060221
- Type: Article
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214
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Boolean satisfiability (SAT) is a core non polynomial (NP)-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. The authors present a hardware solution to the SAT problem. They propose a custom integrated circuit (IC) to implement their approach, in which the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. Further, extracting the minimum unsatisfiable core (i.e. the formula consisting of the smallest set of clauses of the initial formula which is unsatisfiable) is also a computationally hard problem. The proposed hardware approach, in addition to solving SAT, efficiently extracts the minimum unsatisfiable core for any unsatisfiable formula. To the best of the authors' knowledge, this is the first hardware-based solution proposed for extracting the unsatisfiable core. In this approach, clause literals are stored in specially designed clause cells. Clauses are implemented in banks, in a manner that allows clauses of variable width to be accommodated in these banks. To maximise the utilisation of these banks, the authors initially partition the SAT problem. Their solution has significantly larger capacity than existing hardware SAT solvers, and is scalable in the sense that several ICs can be used to simultaneously operate on the same SAT instance. The area, power and performance figures are derived from layout and SPICE (using extracted parasitics) estimates. The approach presented has been functionally validated in Verilog. Preliminary results demonstrate that the approach can accommodate instances with approximately 63 K clauses on a single IC of size 1.5 cm×1.5 cm. This hardware based-SAT solving approach results in over three orders of magnitude speed improvement over Boolean constraint propogation-based software SAT approaches (one to two orders of magnitude over other hardware SAT approaches). The capacity of this approach is significantly higher than most hardware-based approaches. Further, the worst case power consumption was found to be ≤1 mW for the implementation. - Author(s): T. Sasaki ; Y. Ichikawa ; T. Hironaka ; T. Kitamura ; T. Kondo
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 230 –238
- DOI: 10.1049/iet-cdt:20070130
- Type: Article
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A methodology for low‐energy and high-performance computing that is essential in mobile and ubiquitous computing is proposed. The dynamic voltage scaling (DVS) is one of the current major methodologies for low-power devices. However by DVS, the lower the chip voltage becomes in the future, the less energy saving is obtained by DVS. Therefore in order to reduce the energy consumption for lower voltage devices, variable stages pipeline (VSP) processor with the latch D-FF selector (LDS)-cell that unifies pipeline stages dynamically and also decreases energy consumption caused by glitch propagations on a low-energy mode is proposed. With its features, the VSP technique can achieve low-energy computing without any dependence on chip voltage. It is shown that the VSP processor can achieve low-energy computing and higher performance computing than the DVS processor in the low-energy mode by evaluating the proposed approach using SpecINT2000 benchmark suite. - Author(s): K.-C. Chang and T.-F. Chen
- Source: IET Computers & Digital Techniques, Volume 2, Issue 3, p. 239 –249
- DOI: 10.1049/iet-cdt:20070049
- Type: Article
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p.
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As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. Many application-specific systems on chips (SoCs) involve heterogeneous cores with varied functionality and communication requirements, such as those in mobile-phone systems. If a regular network-on-chip is designed to fit the requirements of few high-communicative components, it will be largely over-designed with respect to the needs of the remaining components. Consequently, irregular network architectures might be necessary for realising application-specific SoCs. The authors propose a power-aware topology construction method, which can construct application-specific low-power interconnection topologies according to the traffic characteristics of SoCs. They take several multimedia applications as case studies and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. They also implement a simulator to experiment more general large scale systems, and the results show that customised irregular networks are clearly superior to traditional regular architectures in terms of performance and energy.
Test data compression for system-on-a-chip using extended frequency-directed run-length code
Hardware architecture for high-speed real-time dynamic programming applications
Self-routing, reconfigurable and fault-tolerant cell array
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction
Evaluation of low-energy and high-performance processor using variable stages pipeline technique
Low-power algorithm for automatic topology generation for application-specific networks on chips
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