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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 2, Issue 3, May 2008

Volume 2, Issue 3

May 2008

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    • Test data compression for system-on-a-chip using extended frequency-directed run-length code
      Hardware architecture for high-speed real-time dynamic programming applications
      Self-routing, reconfigurable and fault-tolerant cell array
      Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
      Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures
      Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction
      Evaluation of low-energy and high-performance processor using variable stages pipeline technique
      Low-power algorithm for automatic topology generation for application-specific networks on chips

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