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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 13, Issue 5, September 2019

Volume 13, Issue 5

September 2019

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    • Throughput/area optimised pipelined architecture for elliptic curve crypto processor
      Updating the sets of target faults during test generation for multiple fault models
      High performance and predictable memory controller for multicore mixed-criticality real-time systems
      Approach of genetic algorithm for power-aware testing of 3D IC
      Efficient spiking neural network training and inference with reduced precision memory and computing
      Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator

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