In the real-time systems domain, time-randomised caches have been proposed as a way to simplify software timing analysis, i.e. the process of estimating the probabilistic worst case execution time (pWCET) of an application. However, the technology scaling of the cache memory manufacturing process is rendering transient and permanent faults more and more likely. These faults, in turn, affect a system's timing behaviour and the complexity of its analysis. In this study, the authors propose a static probabilistic timing analysis approach for time-randomised caches that is able to account for the presence of faults – and their detection mechanisms – using a state-space modelling technique. Their experiments show that the proposed methodology is capable of providing tight pWCET estimates. In their analysis, the effects on the estimation of safe pWCET bounds of two online mechanisms for the detection and classification of faults, i.e. a rule-based system and dynamic hidden Markov models (D-HMMs), are compared. The experimental results show that different mechanisms can greatly affect safe pWCET margins and that, by using D-HMMs, the pWCET of the system can be improved with respect to rule-based detection.

In this study, the authors propose a new group testing based (GTB) error control codes (ECCs) approach for improving the reliability of memory structures in computing systems. Compared with conventional single- and double-bit error correcting codes, the GTB codes provide higher reliability at the multi-byte error correction granularity. The proposed codes are cost-efficient in their encoding and decoding procedures. Instead of requiring multiplication or inversion over Galois finite field like most multi-byte ECC schemes, the proposed technique only involves bitwise XOR operations, therefore, significantly reducing the computation complexity and latency. For instance, to correct m errors in a Q-ary codeword of length N, where , the compute complexity is mere . The GTB codes trade redundancy for encoding and decoding simplicity, and are able to achieve better code rate than other ECCs of the same trade-off. The proposed GTB codes lend themselves well to designs with high reliability and low computation complexity requirements, such as storage systems with strong fault tolerance, or compute systems with straggler tolerance, and so on.

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

Production of correct bioassay outcome is the foremost objective in digital microfluidic biochips (or DMFBs). In high-frequency DMFBs, continuous actuation of electrodes leads to malfunctioning or even breakdown of the system. The improper functioning of a biochip tends to produce erroneous results. On the other hand, while transporting droplets, the residues may get stuck to electrode walls and cause contamination to other droplets. To ensure proper assay outcome, washing becomes mandatory, whose incorporation may delay the bioassay completion time significantly. Furthermore, each wash droplet possesses a capacity constraint within which the residues can be washed off successfully. Evidently, the design objectives possess a large degree of trade-offs among themselves and must be attacked to prepare an efficient platform. Here, the authors propose a complete fluid-level synthesis considering all the essential goals together instead of dealing with them in isolation. The presented approach effectively handles the trade-off scenarios and provides flexibility to the designer to decide the threshold of the individual optimisation objective leading to the construction of a good-quality solution as a whole. The performance is evaluated over several benchmark bioassays.

Video recognition applications running on Graphics Processing Unit are composed of heterogeneous software portions, such as kernels or layers for neural networks. The authors propose the concepts of kernel vulnerability factor (KVF) and layer vulnerability factor (LVF), which indicate the probability of faults in a kernel or layer to affect the computation. KVF and LVF indicate the high-level portions of code that are more likely, if corrupted, to impact the application's output. KVF and LVF restrict the architecture/program vulnerability factor analysis to specific portions of the algorithm, easing the criticality analysis and the implementation of selective hardening. We apply the proposed metrics to two Histogram of Oriented Gradients (HOG), and You Only Look Once (YOLO) benchmarks. We measure the KVF for HOG by using fault-injection at both the architectural level and high level. We propose for HOG an efficient selective hardening technique able to detect 85% of critical errors with an overhead in performance as low as 11.8%. For YOLO, we study the LVF with architectural-level fault-injection. We qualify the observed corrupted outputs, distinguishing between tolerable and critical errors. Then, we proposed a smart layer duplication that detects more than 90% of errors, with an overhead lower than 60%.

Stochastic computing (SC) computes with probabilities using randomised bit-streams and standard logic circuits. Its major advantages include ultra-low area and power, coupled with high error tolerance. However, due to its randomness features, SC's accuracy is often low and hard to control, thus severely limiting its practical applications. Random fluctuation errors (RFEs) in SC data are a major factor affecting accuracy, and are usually addressed by increasing the bit-stream length N . However, increasing N can result in excessive computation time and energy consumption, counteracting the main advantages of SC. In this work, the authors first observe that many SC designs heavily rely on constant inputs, which contribute significantly to RFEs. They then investigate the role of constant inputs in SC and propose a systematic algorithm constant elimination algorithm for suppression of errors to eliminate the constant-induced RFEs by introducing memory elements into the target circuits. The resulting optimal modulo-counting (OMC) circuits remove all constant inputs and, at the same time, minimise RFEs. Analytical and experimental results are presented demonstrating other aspects of OMC circuits, including their initialisation and autocorrelation properties, as well as their optimality in terms of minimising RFEs.

In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors’ results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

In distributed systems there is often a need to store and share sensitive information (e.g., encryption keys, digital signatures, login credentials etc.) among the devices. It is also generally the case that this piece of information cannot be entrusted to any individual device since the malfunction or compromising of one node could jeopardize the security of the entire system. Even if the information is split among the devices, there is still a risk when an attacker can compromise a group of them. Therefore we have designed and implemented a secure and robust secret sharing scheme to enable a more resilient sharing of confidential information. This solution provides three important features: (i) it uses threshold secret sharing to split the information into shares to be kept by all devices in the system; so the information can only be retrieved collaboratively by groups of devices; (ii) it guarantees the privacy of the confidential information under a certain number of passive hijacking attacks; and (iii) it ensures the integrity of the confidential information against any number of hijackers who actively and collusively attack the devices. It is able to identify all the compromised devices, while still keeping the secret unforgeable to attackers.

The SER of the selected circuits can be determined via radiation tests. However, the time and costs required to perform radiation tests are prohibitive. Here, the authors introduce an accelerated Monte–Carlo fault injection (MCFI) method that can solve the slow execution time problem of the previous MCFI method using a modified simulator that uses the Verilog Procedural Interface (VPI). To demonstrate the performance of authors’ accelerated MCFI tool, the authors perform a fault-injection campaign using the ISCAS85 and ITC99 benchmark circuits. Compared with the results from previous studies, the authors obtain an accurate logical derating rate value with a 3% variance, and the authors accelerate the execution time by 20 times or more.

This paper proposes an extended two-dimensional mesh Network-on-Chip architecture for region-based fault tolerant routing methods. The proposed architecture has an additional track of links and switches at the four sides of a mesh network so that it can partially reconfigure the network around faulty regions to provide new detour paths. This allows to simplify the complex routing rules of the existing fault-tolerant routing methods and avoid long detour routing paths. Modified routing method is also proposed for the new architecture and the deadlock freeness is proved. Simulation results show that the proposed architecture with the modified routing method reduces the average communication latency by about 39% compared to the existing state-of-the-art method at the expense of low hardware overhead.

The transient error is the failure of the device due to transient hardware faults caused by high-energy particles like neutron and alpha particle strikes. In this study, the authors propose two schemes of fault-tolerant architecture. The first scheme is a hardware-based solution called REMO that combines the best features of space and time redundancy. REMO provides very high fault coverage with minimum overheads in performance, power and area. The second scheme, REMORA combines the best features of hardware and software approaches of fault tolerance. The persistent issue of unprotected code which exists in software approaches is eliminated in this proposal. Simulation results from a SPEC2006 benchmark suite indicate, REMO incurs an increase in the area of about 6%, power overhead is 9% in spite of redundant execution and a negligible performance penalty during a fault-free run. In REMORA, performance degradation increases to 12%. The code size inflation is close to 12%. This is due to the additional signature instructions inserted into the application program. In this study, the authors have explored the possibility of eliminating this penalty by embedding the signatures in control flow instructions. The power and area overhead of REMORA is on par with REMO.

Aggressive technology scaling has inevitably led to reliability becomes a major concern for modern high-speed and high-performance integrated circuits. The major reliability concerns in nanoscale very-large-scale integration design are the time-dependent negative bias temperature instability (NBTI) degradation. Owing to increasing vertical oxide field and higher operating temperature, the threshold voltage of P-channel MOS transistors increases with time under NBTI. This study presents a novel subthreshold Darlington pair-based NBTI degradation sensor under the stress conditions. The proposed sensor provides the high degree of linearity and sensitivity under subthreshold conditions. The Darlington pair used in the circuit provides the stability and the high-input impedance of the circuit makes it less affected by the process variations. Owing to high sensitivity, the proposed sensor is best suited for sensing of temperature variation, process variation, and temporal degradation during measurement. The sensitivity of the proposed sensor at room temperature is 0.239 mV/nA under subthreshold conditions. The proposed sensor is less affected by the process variation and has the maximum deviation of 0.0011 mV at standby leakage current of 30 nA.

With continued scaling of integrated circuits into deep nanoscale fabrication technologies, the aggravated effects of reliability degradation and variability in process parameters can hinder effective yields. Fortunately, due to the immense flexibility of contemporary reconfigurable hardware (RH), reconfiguration-based resilience can be exploited to effectively tackle such challenges. Nonetheless, reconfiguration-based resiliency is typically limited due to the complexity of the fault resolution space, interconnect routing constraints, and dynamic reconfiguration time in situ. These challenges are addressed herein by deriving a pre-emptive design approach based on union-free hypergraphs, which can define distinct physical implementations with highly separable subsets of the target device's resources covering the largest solution space feasible for reliability exposures and uncertain parametric variations. Two scalable and highly transportable algorithms to realise union-free hypergraphs are introduced and investigated. Hardware demonstration on a commercial-grade field programmable gate array platform shows a significant increase in fault tolerance compared to commonly-used modular redundancy methods. Furthermore, Monte-Carlo statistical results across a set of benchmarks show an average improvement in critical path delay of 6.8, 8.6, and 10.8% for combined variations of 15, 25, and 35%, respectively, while achieving a net reduction in performance variation impact of 34.8, 38, and 41% for identical levels of variability.

The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR-based circuits can have an over 50% yield advantage over their synchronous counterparts.