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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 13, Issue 3, May 2019


Volume 13, Issue 3

May 2019

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    • Probabilistic timing analysis of time-randomised caches with fault detection mechanisms
      Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes
      Scheduling configuration memory error checks to improve the reliability of FPGA-based systems
      Fluid-level synthesis unifying reliability, contamination avoidance, and capacity-wastage-aware washing for droplet-based microfluidic biochips
      Kernel and layer vulnerability factor to evaluate object detection reliability in GPUs
      Removing constant-induced errors in stochastic circuits
      HASTI: hardware-assisted functional testing of embedded processors in idle times
      RASSS: a hijack-resistant confidential information management scheme for distributed systems
      Study of the monte–carlo fault injection simulator to measure a fault derating
      Design of an extended 2D mesh network-on-chip and development of A fault-tolerant routing method
      Soft-error reliable architecture for future microprocessors
      SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit
      Leveraging design diversity to counteract process variation: theory, method, and FPGA toolchain to increase yield and resilience in-situ
      Yield modelling and analysis of bundled data and ring-oscillator based designs

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