Simulation-based sequential test generation procedures address the high computational complexity of sequential test generation by replacing the deterministic branch-and-bound process with lower-complexity processes. These processes introduce new primary input patterns into a functional test sequence in order to increase its fault coverage. This study observes that, even without introducing new primary input patterns, it is possible to increase the fault coverage of a functional test sequence by applying the same primary input patterns in different orders. This is referred to as reconstruction of the sequence. It provides a new low-complexity option for increasing the fault coverage, and thus addressing the high computational complexity of sequential test generation. This study describes a reconstruction procedure that is based on repeating short subsequences of primary input patterns from the sequence. Experimental results demonstrate the effectiveness of the reconstruction procedure in increasing the fault coverage as part of a simulation-based sequential test generation procedure.

Several test generation procedures are based on the expectation that after clocking a circuit in functional mode for several clock cycles, the circuit enters its functional state space and operates under functional operation conditions. Functional operation conditions are important for avoiding overtesting of delay faults. This study develops a quantitative metric for assessing the ability of functional capture cycles to take the circuit into its functional state space, and ensure functional operation conditions. The metric is based on the distances between the states that the circuit traverses during functional capture cycles and reachable states that the circuit can enter during functional operation. The paper also describes a procedure for modifying a test set so as to reduce the values of the metric for its tests.

Adaptive filters are prevalent in many real-time signal processing applications. Many adaptive algorithms already exist, but most of them assume white Gaussian noise as disturbance. However, for many applications such as electrocardiogram, foetus heart rate measurement, low frequency atmospheric noise, underwater acoustic noise and signal measurement in instrumentation, the impulsive noise is more common. This study presents a modified robust mixed norm (MRMN) adaptive filter algorithm robust to impulsive noise with higher convergence rate and lower steady state error (SSE). MRMN adaptive filter algorithm has been simulated using Matlab and Xilinx system generator high level synthesis tool and a significant improvement in SSE and convergence speed is obtained compared with the existing adaptive filter algorithms for similar specifications. The proposed algorithm is also described using VHDL and synthesised using Xilinx synthesiser tool in order to implement on field-programmable gate array (FPGA). The FPGA post route and place implementation results show nearly 90% reduction in resource utilisation and nearly 2.6 times improvement in clock frequency as compared with the existing FPGA based implementation for similar specifications.

Field programmable gate arrays (FPGAs) are adopted in many electronic systems, due to their design flexibility and high performance. For providing right FPGAs for different applications, FPGA architectural exploration is needed. Accurate estimation of area and delay of low-level FPGA circuits is required to evaluate different architecture candidates during the exploration. In this study, the authors present a fast and accurate delay model by extracting the key parameters affecting FPGA delay and by combining the classical Elmore equivalent model and the powerful learning capability of neural network. The derived model can be integrated with the existing FPGA architecture exploration flow perfectly. Experimental results show that compared with circuit simulator tool HSPICE, this model speeds up the delay estimation by 2863 times with the average error of 1.9% during the architectural exploration process. This fast and accurate estimation allows FPGA architects to explore more architectural options in limited time, resulting in optimised FPGA architecture.