Digital multiplier and squarer circuits are indispensable in digital signal processing and cryptography. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be simpler with less amount of hardware, propagation delay and power consumption. Our work proposes an efficient algorithm using literals minimisation technique to achieve squaring with improved performance with respect to area, delay and power. This technique compares favourably with the recent work by offering less gate delay, transistor count and area. The proposed optimisation algorithm has been verified using different Xilinx and Altera Field Programmable Gate Array device family. Simulation results show better performance of our technique than the work shown in the past work in respect of delay, power and area. Moreover the proposed technique has been compared with the well known Radix-4 Booth encoded squarer technique. Further, application specific integrated circuit (ASIC) implementation has been performed and the performance parameters have been compared with the earlier work and that also establishes the better results for our technique.

The IEEE 802.11ac is the recently ratified standard developed for the fifth generation wireless fidelity technology, in which the multi-user (MU) multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) technique is adopted for the high data rate communication. In an MIMO-OFDM System, the forward/inverse fast Fourier transform (FFT/IFFT) processor is a key component. On proper reception, the reordering and scheduling of data is important for the optimal utilisation of butterfly resources in the pipelined FFT/IFFT processor. In this study, a mathematical model for an eight-parallel multimode (N = 512/256/128/64) multi-path delay commutator-based FFT/IFFT processor which is suitable for the IEEE 802.11ac compliant MU-MIMO-OFDM system is presented. On the other hand, the data reordering, scheduling methodologies and its architectures are proposed for the pre-, post-FFT/IFFT process are proposed. The design implementations are done using TSMC 65 nm complementary metal–oxide–semiconductor technology at 160 MHz. The power and area metrics with and without clock gating are compared. The clock gated implementation reports show that the power consumption is 17.44 mW for the pre-transformed data reordering and 11.64 mW for the post-transformed data reordering with an area occupation of 0.7694 mm² and 0.5111 mm², respectively.

The number of cores on a chip is increasing from a few cores to thousands. However, the communication mechanisms for these systems do not scale at the same pace, leading to certain challenges. One of them is on-chip congestion. There are many table-based approaches for congestion handling and avoidance, but these are not acceptable as they impose high area and power overheads. In this study, the authors propose two congestion handling strategies aiming to capture the congestion in few bits to avoid congested routes. The first approach called σ ⁿ LBDR (logic based distributed routing) captures congestion present at nodes n-hop away from the current node, reducing area, power and overall packet latency. However, all nodes in the network do not experience same congestion level. For this, their second approach, weighted σ ⁿ LBDR, uses a different set of bits for each node and results in the further improvement in area and power. This study shows a comparison of both approaches with each other and also with other similar approaches. From their experimental results, they show that σ ⁿ LBDR and weighted σ ⁿ LBDR improve latency by 20 and 30%, respectively, and have less area and power overhead as compared with baseline table-based approach.

Digital microfluidic biochip's (DMFB's) have emerged as an alternative to various in-vitro diagnostic tests and are expected to be closely coupled with cyber physical systems. Efficient-error-free-routing and cross-contamination minimisation are needed during bioassay operations on DMFB. This study proposes a two phase heuristic technique for routing droplets on a two-dimensional DMFB. Initially it attempts to route maximum number of nets in a concurrent fashion depending on the evaluated value of a proposed function named interfering index (II_net). Then exact routing is attempted based on tabulation minimisation process. Remaining nets having interfering index values higher than threshold will be routed considering various constraints in DMFB framework. In second phase another metric named routable ratio (RR) is proposed and depending on RR metric, the routing order among conflicting paths are prioritised to avoid deadlock from there onwards till the droplet reaches its target location. Finally we formulate droplet movement problem as satisfiability problems and solve with SAT based solver engine if higher number of overlapping (≥5) nets exist. Experimental results on benchmark suite I and III show our proposed technique significantly reduces latest arrival time, average assay execution time and number of used cells as compared with earlier methods.

Digital microfluidic biochips are reforming many areas of biochemistry, biomedical sciences, as well as microelectronics. It is renowned as lab-on-a-chip for its appreciation as a substitute for laboratory experiments. Nowadays, for emergency purposes and to ensure cost efficacy, multiple assay operations are essential to be carried out simultaneously. In this context, parallelism is of utmost importance in designing biochip while the size of a chip is a constraint. Hence, the objective of this study is to enhance the performance of a chip in terms of its throughput, electrode utilisation, and pin count as well. Here, the authors have considered some of the most familiar assay requirements where a sample is to be analysed using different reagents, and identify some parameter(s) of the sample(s) under consideration. Moreover, sample preparation is a vital task in digital microfluidic biochip; thus, dilution of different samples up to different concentrations using buffer (neutral) fluid is a crucial issue. In this design, the authors effectively perform this task in parallel in a number of sub-regions of a given restricted sized chip using an array based partitioning pin-assignment technique while taking care of the cross contamination problem. The design has been verified for some significant real life assay examples.

A fully integrated, low power low-noise amplifier (LNA) is implemented for 2.14 GHz band using 65-nm radio frequency CMOS technology. By taking advantage of higher transition frequencies of recent technologies, transistors are biased in the moderate inversion region thus permitting scaling down the supply voltage to 0.7 V. Further, the exploration of design spaces from strong to weak inversions assisted the development of a unified noise factor model. An optimisation is carried out based on the parameter extraction and accordingly an extraction methodology is developed. Overall, the unified model based on the parameter extraction helped in noise estimation in all regions of inversion. The resulting LNA achieves a good power match at the input where the simulated S11 parameter shows an excellent value of −22 dB. Compared to other existing subthreshold cascode LNAs reported in the literature, it shows reasonably better performance in terms of noise and power consumption with a noise figure of 3.74 dB and a moderate power gain of 8.7 dB at a core device current consumption of 450 μA.

In this paper, a design of two microelectromechanical systems based devices is carried out using an analytical and finite-element analysis. The first device is mechanically coupled ring-resonator band-pass filter with centre frequency of 4.4 MHz and a small bandwidth of only 36 kHz. Flexural-mode ring resonators have been mechanically coupled using soft mechanical spring for realising the filtering action. Owing to inherent symmetry in the ring structure, simple approach is used to access a low-velocity coupling locations to set a smallest possible bandwidth. The authors also show a reduction in the amplitude of spurious mode by accentuating the filter structure in its fully differential mode inherently present in the structure. Moreover, the effect of the number of the support beams and structural damping on the frequency response of a filter has been analysed. A second device is mechanically coupled ring-resonator arrays with varying number of rings coupled. The mechanical links using short stubs connect each constituent resonator of an array to its adjacent ones at the high-velocity vibrating locations to accentuate the desired mode and reject all other spurious modes. Both analytical and finite-element based simulation results for parameters of the designed structure are found in good agreement.

In the present study, temperature drift analysis of metal–oxide–semiconductor field-effect transistor (MOSFET) is carried out using silicon nitride/SiO₂ as dielectric film. An n-channel depletion-mode MOSFET was fabricated with silicon nitride ion-sensitive field-effect transistor (ISFET) on the same wafer. The study presents the fabrication, simulation and characterisation of MOSFET. The gate of the ISFET is stacked with silicon nitride/SiO₂ sensing membrane that was deposited using low pressure chemical vapour deposition. Output and transfer characteristics of on-chip fabricated Al gate MOSFET were obtained in order to study the fabricated ISFET behaviour to be used as pH sensor. Silicon nitride is preferred over SiO₂ sensing film/dielectric (in case of MOSFET) which has better sensitivity and low drift. Process and device simulations were performed using Silvaco® TCAD tool.

In this study, electrically doped bio-molecular p-i-n field-effect transistor (FET) is designed and its electronic properties are investigated. Density functional theory along with non-equilibrium Green's function based first principle approach is used to design the bio-molecular FET at sub-atomic region. Three Adenine and two Thymine molecules are attached together to form 6.24 nm long and 1.40 nm wide bio p-i-n FET. This device is attached with two platinum electrodes and wrapped with a metallic cylindrical gate at high vacuum. Intrinsic n and p regions can be made possible within a bio-molecular device at room temperature by electrical doping without explicit dopants, which leads to conduct current by the device both in forward and reverse bias. The various quantum mechanical properties have been calculated using Poisson's equations and self-consistent function for the bio-molecular FET. Among these various quantum mechanical properties, the authors obtain high quantum transmission along with satisfactory current for the proposed device during the room temperature operation. The goal of this study is to highlight the design of a bio-molecular p-i-n FET with satisfactory large current using ultra low power dissipation.