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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 1, Issue 5, September 2007


Volume 1, Issue 5

September 2007

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    • Editorial: Design of circuits and integrated systems
      A digital system to emulate wireless networks
      Towards a configurable SoC MPEG-4 advanced simple profile decoder
      Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
      Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures
      Charge-based testing BIST for embedded memories
      Functional-oriented mask-based built-in self-test
    • Editorial: Advances in electronics systems simulation
      Simulation and development environment for mobile 3D graphics architectures
      Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulink® mixed environment
      Modelling tools built upon the hardware description language foundation
      Modelling and simulation techniques for highly integrated, low-power wireless sensor networks
    • Effectiveness of scan-based delay fault tests in diagnosis of transition faults
      Admitting and ejecting flits in wormhole-switched networks on chip
      Algorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures
      Memory hierarchy for high-performance and energy-aware reconfigurable systems
      Enhanced prefix inclusion coding filter-encoding algorithm for packet classification with ternary content addressable memory
      Design and simulation of reusable IP CORDIC core for special-purpose processors
      On-chip bus thermal analysis and optimisation
      VLSI architecture and chip for combined invisible robust and fragile watermarking
      Fast and memory-efficient invariant computation of ordinary Petri nets
      Fast INC-XOR codec for low-power address buses
      High-performance scalable bidirectional mixed radix-2n serial–serial multipliers
      Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation
      Energy-delay efficient test

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