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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 1, Issue 4, July 2007

Volume 1, Issue 4

July 2007

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    • Editorial: Field-programmable logic and applications
      Statistical placement for FPGAs considering process variation
      Multi-layer floorplanning for reconfigurable designs
      Server-based execution of periodic tasks on dynamically reconfigurable hardware
      Exploiting parallelism in configurable architectures through custom array mapping
      Non-uniform random number generation through piecewise linear approximations
    • Low overhead DFT using CDFG by modifying controller
      Optimising power efficiency in trace cache fetch unit
      High performance physical random number generator
      Worst-case and average-case analysis of n-detection test sets and test generation strategies
      Efficient test compaction for combinational circuits based on Fault detection count-directed clustering
      Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing
      Binary-coded decimal digit multipliers
      Four-level realisation of 3-qubit reversible functions
      High speed hardware architecture to compute galois fields GF(p) montgomery inversion with scalability features
      Novel low-overhead roll-forward recovery scheme for distributed systems
      Dynamic global security-aware synthesis using SystemC
      Low error fixed-width two's complement squarer design using Booth-folding technique
      Hardware accelerated constrained random test generation
      Finite state machine-based DRAM power management with early resynchronisation

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