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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 1, Issue 1, January 2007

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Volume 1, Issue 1

January 2007

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    • System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies
      • Author(s): N. Wang  and  M.A. Bayoumi
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 1, p. 1 –8
      • DOI:  10.1049/iet-cdt:20060080
      • Type: Article
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      • p. 1 –8 (8)
        Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution schemes for managing simultaneous access requests to the communication resources are required to prevent system performance degradation. A new SOC on-chip communication architecture, Dynamic Parallel Fraction Control Bus, which offers an attractive solution for the problem and addresses shortcomings of existing communication architectures is presented. To demonstrate the benefits of the proposed architecture, several existing communication architectures were compared with the proposed architecture on the basis of two application prototypes. Through experimentation it has been shown that the proposed architecture not only exhibits both hardware simplicity and system performance improvements, but also produces better bus bandwidth control and scalability properties compared with the existing communication architectures.
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      Optimised realisations of large integer multipliers and squarers using embedded blocks
      • Author(s): S. Gao ; N. Chabini ; D. Al-Khalili ; P. Langlois
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 1, p. 9 –16
      • DOI:  10.1049/iet-cdt:20060074
      • Type: Article
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      • p. 9 –16 (8)
        An efficient design methodology and a systematic approach for the implementation of multiplication and squaring functions for unsigned large integers, using small-size embedded multipliers are presented. A general architecture of the multiplier and squarer is proposed and a set of equations is derived to aid in the realisation. The inputs of the multiplier and squarer are split into several segments leading to an efficient utilisation of the small-size embedded multipliers and a reduced number of required addition operations. Various benchmarks were tested for different segments ranging from 2 to 5 targeting Xilinx Spartan-3 FPGAs. The synthesis was performed with the aid of the Xilinx ISE 7.1 XST tool. The approach was compared with the traditional technique using the same tool. The results illustrate that the design approach is very efficient in terms of both timing and area savings. Combinational delay is reduced by an average of 7.71% for the multiplier and 21.73% for the squarer. In terms of 4-inputs look-up tables, area is lowered by an average of 11.63% for the multiplier and 52.22% for the squarer. In the case of the multiplier, both approaches use the same number of embedded multipliers. For the squarer, the proposed approach reduces the number of required embedded multipliers by an average of 32.77% compared with the traditional technique.
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      ROM to DSP block transfer for resource constrained synthesis
      • Author(s): G.W. Morris ; G.A. Constantinides ; P.Y.K. Cheung
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 1, p. 17 –26
      • DOI:  10.1049/iet-cdt:20060016
      • Type: Article
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      • p. 17 –26 (10)
        Modern field programmable gate array (FPGA) architectures are moving towards heterogeneity with the increasing inclusion of coarse grained elements such as embedded multipliers and RAMs. This has given rise to a multi-dimensioned resource-based measure of design area, very different from the traditional application-specific integrated circuit figure of silicon area. In order for a designer to use these heterogenous elements in their design, they must usually specifically instantiate them. Heterogeneous elements not used in a design remain unused on the device, consuming leakage power, silicon area and manufacturing costs. Method of transferring functionality normally implemented in embedded ROMs and 4-input look-up tables (4-LUTs) onto unused digital signal processor (DSP) blocks is proposed. The paper proceeds to include this method in a synthesis system incorporating the idea of resource constrained synthesis, where a design is mapped to an FPGA considering user and device constraints on heterogenous element usage, based on an extension to the Altera Quartus II synthesis software. Results have been obtained, showing an improvement over existing methods in 76% of the 21 ROMs examined. Further results have been obtained from applying this approach with the synthesis system to benchmark algorithms. In the designs examined, the number of possible implementations has increased by two to four times over Altera Quartus.
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      Test data truncation for test quality maximisation under ATE memory depth constraint
      • Author(s): E. Larsson  and  S. Edbom
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 1, p. 27 –37
      • DOI:  10.1049/iet-cdt:20050209
      • Type: Article
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      • p. 27 –37 (11)
        Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.
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      RNS multiplication/sum-of-squares units
      • Author(s): D. Adamidis  and  H.T. Vergos
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 1, p. 38 –48
      • DOI:  10.1049/iet-cdt:20060009
      • Type: Article
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      • p. 38 –48 (11)
        Digital signal processing and multimedia applications often profit from the use of a residue number system. Among the most commonly used moduli, in such systems, are those of 2n−1 and 2n+1 forms and among the most commonly used operations are multiplication and sum-of-squares. These operations are currently performed using distinct design units and/or consecutive machine cycles. Novel architectures for combined units that perform modulo 2n−1/diminished-1 modulo 2n+1 multiplication or sum-of-squares depending on the value of a control signal are proposed.
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      Design of efficient modulo 2n+1 multipliers
      • Author(s): H.T. Vergos  and  C. Efstathiou
      • Source: IET Computers & Digital Techniques, Volume 1, Issue 1, p. 49 –57
      • DOI:  10.1049/iet-cdt:20060026
      • Type: Article
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      • p. 49 –57 (9)
        A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions.
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