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Online ISSN 1751-861X Print ISSN 1751-8601

IET Computers & Digital Techniques

Volume 1, Issue 1, January 2007

Volume 1, Issue 1

January 2007

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    • System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies
      Optimised realisations of large integer multipliers and squarers using embedded blocks
      ROM to DSP block transfer for resource constrained synthesis
      Test data truncation for test quality maximisation under ATE memory depth constraint
      RNS multiplication/sum-of-squares units
      Design of efficient modulo 2n+1 multipliers

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