Hardware Trojan detection techniques have been studied extensively. However, to develop reliable and effective defenses, it is important to figure out how hardware Trojans are implemented in practical scenarios. The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook. Unlike all previous surveys that discuss Trojans from the defender's perspective, for the first time, the authors study the Trojans from the attacker's perspective, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan. First, the authors present adversarial models in terms of the adversary's methods, adversary's capabilities, and adversary's challenges in seven practical hardware Trojan implementation scenarios: in-house design team attacks, third-party intellectual property vendor attacks, computer-aided design tools attacks, fabrication stage attacks, testing stage attacks, distribution stage attacks, and field-programmable gate array Trojan attacks. Second, the authors analyse the hardware Trojan implementation methods under each adversarial model in terms of seven aspects/metrics: hardware Trojan attack scenarios, the attacker's motivation, feasibility, detectability (anti-detection capability), protection and prevention suggestions for the designer, overhead analysis, and case studies of Trojan implementations. Finally, future directions on hardware Trojan attacks and defenses are also discussed.

Discrete wavelet transform (DWT) is widely used in the image and video compression due to its high compression ratio and resolution. This study proposes efficient very large scale integration (VLSI) architectures of lifting based 3D-DWT using (5,3) and (9,7) Daubechies wavelets. The advantage of these proposed architectures is the absence of storage buffer in between the row, column, and temporal processes. Also, five and nine numbers of frames of the 3D signal can be processed in parallel using the proposed (5,3) and (9,7) lifting based DWTs, respectively. Due to this parallelism and the elimination of storage buffers, the throughput of the proposed design is greater than other existing techniques. The authors have implemented all the existing and proposed 3D-DWTs using 45 nm CMOS library with Cadence and Artix-7 FPGA with Xilinx Vivado. The synthesis results show that the proposed designs achieve significant improvement in throughput than various existing designs. For example, the proposed (9,7) lifting based 3D-DWT achieves 85.4% of improvement in the throughput than the conventional design.

High-efficiency video coding (HEVC) is the latest video coding standard aimed to reduce the bitrate by half for the same video quality compared to H.264/AVC. This encoding performance makes HEVC more suitable for high-definition video applications. However, this performance is coupled with a high-computational complexity, which makes it hard to achieve real-time video encoding with a classic embedded processor. Multicore technology of programmable processors could be a very promising solution to overcome this computational complexity. Moreover, software optimisations by proposing fast algorithms for the most complex functions could also be an efficient solution to speed up the encoding process. In this context, this study presents a fast mode decision algorithm for the intra prediction module. This algorithm aims to reduce the number of intra prediction modes to be tested instead of performing a full intra mode search. Experimental results for all-Intra configuration show that the proposed fast intra mode decision allows saving up to 46.79% of the intra prediction time in average. Encoding performance in terms of video quality and bitrate is not significantly affected.

The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on-chip interconnects has been demonstrated. Subsequently, a novel time-efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through-silicon-via (TSV), which is used to connect different dies vertically in a 3D IC. Under high-frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.

With the development of network-on-chip (NoC) theory, lots of mapping algorithm have been proposed to solve the application mapping problem which is an NP-hard (non-polynomial hard) problem. Most algorithms are based on a heuristic algorithm. They are trapped by iterations limited, not by the distance between iterations, because of the isomorphism of mapping sequence. In this study, the authors define and analyse the isomorphism with the genetic algorithm (GA) which is a heuristic algorithm. Then, they proposed an approach called density direction transform algorithm to eliminate the isomorphism of mapping sequence and accelerate the convergence of population. To verify this approach, they developed a density-direction-based genetic mapping algorithm (DDGMAP) and make a comparison with genetic mapping algorithm (GMA). The experiment demonstrates that compared to the random algorithm, their algorithm (DDGMAP) can achieve on an average 23.48% delay reduction and 7.15% power reduction. And DDGMAP gets better performance than GA in searching the optimal solution.