A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 ^m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

A comprehensive test set targets the detection of several fault models. As an example, in this study, stuck-at faults, transition faults and four-way bridging faults are targeted. Bridging faults represent a fault model where it is necessary to select a subset of target faults from all the possible faults. After test generation for single stuck-at faults, undetectable single stuck-at faults can be used for identifying undetectable transition and four-way bridging faults. These faults can be removed from the sets of target faults to reduce the test generation effort. The new contribution of the study is related to the possibility of updating the set of target bridging faults again after test generation for transition faults. The analysis performed in the study leads to the premise that the presence of an undetectable or aborted transition fault on a line g makes bridging faults that are associated with line g less likely to be detected. As a result, line g may be covered by fewer bridging faults than selected for it, creating a test hole. To address this issue, the study suggests that more bridging faults should be selected for line g in this case. Experimental results are presented to support the discussion.

Multicore processors are widely used in today's real-time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed-criticality, in which the non-functional requirements of the tasks are different or even conflicting. A major challenge in mixed-criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state-of-the-art memory controllers using gem5 full-system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.