
This journal was previously known as IEE Proceedings - Computers and Digital Techniques 1994-2006. ISSN 1350-2387. more..
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Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
- Author(s): Saeideh Sheikhpur ; Mahdi Taheri ; Mohammad Saeed Ansari ; Ali Mahani
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p.
395
–408
(14)
AbstractDigital data transmission is day by day more vulnerable to both malicious and natural faults. With an aim to assure reliability, security and privacy in communication, a low‐cost fault resilient architecture for Advanced Encryption Standard (AES) is proposed. In order not to degrade the reliability of our AES architecture, the reliability of voter is very important, for which reason we have introduced a novel voting scheme include a majority voter (named TMR voter) and an error barrier element (named DMR voter). In this paper, a reliable and secure 32‐bit data‐path AES implementation based on our robust fault resilient approach is developed. We illustrate that the proposed architecture can tolerate up to triple‐bit (byte) simultaneous faults at each pipeline stage’s logic and verify our claim through extensive error simulations. Error simulation results also show that our architecture achieves close to 100% fault‐masking capability for multiple‐bit (byte) faults. Finally, it is shown that the Application‐Specific Integrated Circuit implementation of the fault‐tolerant architectures using the composite field‐based S‐box, CFB‐AES, and ROM‐based S‐box, RB‐AES allows better area usage, throughput and fault resilience trade‐off compared to their counterparts. So, it provides the most appropriate features to be used in highly‐secure resource‐constraint applications.
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Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow
- Author(s): Mickael Fiorentino ; Claude Thibeault ; Yvon Savaria
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p.
409
–426
(18)
AbstractA self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing‐driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing‐driven synthesis and static timing analysis. Finally, two 32‐bit RISC‐V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock‐gating and SynV without clock‐gating.
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Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture
- Author(s): Xiaoying Huang ; Zhichuan Guo ; Mangu Song ; Xuewen Zeng
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p.
427
–436
(10)
AbstractSM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This study proposes a CPU‐FPGA co‐designed architecture which offloads the SM3 function on field‐programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115‐flva1517‐2‐e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU‐FPGA‐coupled environment.
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High-performance elliptic curve cryptography processor over NIST prime fields
- Author(s): Md Selim Hossain ; Yinan Kong ; Ehsan Saeedi ; Niras C. Vayalil
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Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits
- Author(s): Aiman H. El-Maleh
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Scalable GF(p) Montgomery multiplier based on a digit–digit computation approach
- Author(s): M. Morales-Sandoval and A. Diaz-Perez
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Fabrication and characterisation of Al gate n-metal–oxide–semiconductor field-effect transistor, on-chip fabricated with silicon nitride ion-sensitive field-effect transistor
- Author(s): Rekha Chaudhary ; Amit Sharma ; Soumendu Sinha ; Jyoti Yadav ; Rishi Sharma ; Ravindra Mukhiya ; Vinod K. Khanna
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Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip
- Author(s): Hanmin Park and Kiyoung Choi