IET Computers &amp; Digital Techniques

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Online ISSN 1751-861X
Print ISSN 1751-8601

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.

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RASSS: A Hijack-resistant Confidential Information Management Scheme for Distributed Systems
- Author(s): Lake Bu ; Mihailo Isakov ; Michel Kinsy
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HASTI: Hardware-assisted Functional Testing of Embedded Processors in Idle Times
- Author(s): Arezoo Kamran
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Removing Constant-induced Errors in Stochastic Circuits
- Author(s): Paishun Ting and John P Hayes
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Efficient digital implementation of a multi-precision square-root algorithm
- Author(s): Alexander E. Beasley ; Robert J. Watson ; Christopher T. Clarke
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  In high performance computing systems and signal processing, there is a basic set of mathematical functions that are essential. While addition, subtraction and multiplication are well understood, there is less literature on square-rooting, which is a particularly time- and resource-consuming function. Traditional non-restoring algorithms produce a mantissa half the length of the input mantissa, causing a loss of precision. This study presents a method for increasing the accuracy of this algorithm. It is shown to work for all IEEE-754R standard floating-point numbers. Error analysis shows a 57-fold (for half-precision) and 134e6-fold improvement (for double-precision) in the normalised error, equivalent to at most 1 Units of Least Precision. Resource and performance optimised variants are analysed and their throughput analysed. On an Intel Stratix V device, performance optimised implementations achieve a throughput of 717 MFLOPs. Resource optimised implementations on a low-cost device require only 127 Adaptive Logic Modules and 232 registers, with a throughput of 8.56 MFLOPs. All implementations are DSP block and memory free, saving valuable resources. The maximum throughput of the presented design is 15.5 times greater than that proposed by Pimentel et al. and two orders of magnitude greater than typical multiply-accumulate methods.
Energy-Efficient LDPC Codec Design Using Cost-Effective Early Termination Scheme
- Author(s): Cheng-Hung Lin ; Yuan-Syun Wu ; Chen-Pei Song
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Design of efficient modulo 2ⁿ+1 multipliers
- Author(s): H.T. Vergos and C. Efstathiou
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
- Author(s): M. Fazeli ; S.G. Miremadi ; A. Ejlali ; A. Patooghy
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures
- Author(s): R. Chaves and L. Sousa
Binary-coded decimal digit multipliers
- Author(s): G. Jaberipur and A. Kaivani
VLSI architecture and chip for combined invisible robust and fragile watermarking
- Author(s): S.P. Mohanty ; E. Kougianos ; N. Ranganathan

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Latest content

RASSS: A Hijack-resistant Confidential Information Management Scheme for Distributed Systems

HASTI: Hardware-assisted Functional Testing of Embedded Processors in Idle Times

Removing Constant-induced Errors in Stochastic Circuits

Efficient digital implementation of a multi-precision square-root algorithm

Energy-Efficient LDPC Codec Design Using Cost-Effective Early Termination Scheme

Most downloaded

Most cited

Design of efficient modulo 2ⁿ+1 multipliers

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures

Binary-coded decimal digit multipliers

VLSI architecture and chip for combined invisible robust and fragile watermarking