In a context of increasing demands for on-board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non-utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors’ results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.

The ill effects of process, voltage, and temperature variations are significantly reduced by ring-oscillator (OR)-based clocks and bundled-data (BD) designs. Such designs include delay lines that enable the addition of test margin that can either by set uniformly across all manufactured chips or tuned individually per-chip. This study mathematically analyses the resulting yield subject to a limit on shipped product quality providing a practical mechanism of optimising the test margins for these circuits. The model also provides a means of quantifying the benefits from the correlation in the delay line and combinational logic. In particular, using correlation values obtained from Monte Carlo analysis of a sample circuit in a 65 nm process, the model shows that BD and OR-based circuits can have an over 50% yield advantage over their synchronous counterparts.

Selection strategy is an essential part of an adaptive routing algorithm that influences the performance of the networks-on-chip (NoC). A selection strategy is used for selecting the best output channel from the available channels according to the network status. This study presents a new output selection strategy called destination intensity and congestion aware (DICA) that uses both local and regional congestion information from adjacent and two hops away neighbours on the path to destination based on the channel and switch information. Also, the proposed output selection strategy uses a new global congestion-aware scheme based on destination node called destination congestion awareness method to distribute traffic more equally over the network. The simulation results show that DICA strategy consistently improves the performance in both throughput and average latency with minimal overhead in terms of area consumption for various synthetic and real application traffic patterns. In addition, the microarchitecture of NoC routers is also presented in this study and it shows that the proposed output selection strategy can be combined with any adaptive routing algorithms. The experimental results show the average delay improvements of DICA to the Bufferlevel, neighbours-on-path, and regional congestion awareness are 87, 57, and 24%, respectively.

With continued scaling of integrated circuits into deep nanoscale fabrication technologies, the aggravated effects of reliability degradation and variability in process parameters can hinder effective yields. Fortunately, due to the immense flexibility of contemporary reconfigurable hardware (RH), reconfiguration-based resilience can be exploited to effectively tackle such challenges. Nonetheless, reconfiguration-based resiliency is typically limited due to the complexity of the fault resolution space, interconnect routing constraints, and dynamic reconfiguration time in situ. These challenges are addressed herein by deriving a pre-emptive design approach based on union-free hypergraphs, which can define distinct physical implementations with highly separable subsets of the target device's resources covering the largest solution space feasible for reliability exposures and uncertain parametric variations. Two scalable and highly transportable algorithms to realise union-free hypergraphs are introduced and investigated. Hardware demonstration on a commercial-grade field programmable gate array platform shows a significant increase in fault tolerance compared to commonly-used modular redundancy methods. Furthermore, Monte-Carlo statistical results across a set of benchmarks show an average improvement in critical path delay of 6.8, 8.6, and 10.8% for combined variations of 15, 25, and 35%, respectively, while achieving a net reduction in performance variation impact of 34.8, 38, and 41% for identical levels of variability.