In this paper, a new bi-directional transceiver has been proposed for high-speed signalling across on-chip global interconnects. The proposed transceiver has two modes of operation namely, the transmitter and the receiver. As a result, two transceivers sitting at the two ends of an interconnect can support two-way communication through the same link. The transceiver has very low small-signal impedance for both modes of operation and thereby supports high bandwidth of the link. Moreover, because of its high transimpedance gain over a large bandwidth in the receiving mode, the signalling current can be reduced to a very low value. The circuit has been designed in 65 nm, 1.2 V process with a global interconnect of length 10 mm and width 1.5 μm. Post-layout simulation of the transceivers with the link gives an energy efficiency of 0.101 pJ/b for a data transmission of 14 Gbps.

This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose–Chaudhuri–Hocquenghem (BCH) and outer Reed–Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.

Gaussian normal basis (GNB) of the even-type is popularly used in elliptic curve cryptosystems. Efficient GNB multipliers could be realised by Toeplitz matrix-vector decomposition to realise subquadratic space complexity architectures. In this study, Dickson polynomial representation is proposed as an alternative way to represent an GNB of characteristic two. The authors have derived a novel recursive Dickson–Karatsuba decomposition to achieve a subquadratic space-complexity parallel GNB multiplier. By theoretical analysis, it is shown that the proposed subquadratic multiplier saves about 50% bit-multiplications compared with the corresponding subquadratic GNB multiplication using Toeplitz matrix-vector product approach.

In this paper, a new voltage mirror circuit by using carbon nanotubes (CNTs) technology is presented. This circuit is specifically proposed for the application of duplicating multiple-valued and fuzzy dynamic random access memories. The given structure prevents any voltage drop for the capacitor inside the memory cell. As a result, any fanout circuit can be driven. The new structure can be utilised for different multiple-valued logic systems without a change. The unique characteristics of carbon nanotube field effect transistor (CNFET) technology are exploited in this paper to meet the desired design goals. It demonstrates the potentials of CNFET technology in a realistic very large-scale integration application. The proposed design is highly tolerant to D _CNT variation and it is also immune to misaligned CNTs. Simulation results demonstrate that it provides sufficient driving capability with reasonable accuracy.

To alleviate practical limitations in the design of millimetre-wave on-chip image-reject filters, systematic design methodologies are presented. Three low-order filters with high-selectivity and low-loss characteristics are designed and compared. Transmission zeroes are created by means of a quarter-wave transmission line (filter 1) and a series LC resonator (filters 2 and 3). Implemented on silicon germanium, the filters occupy 0.125, 0.064 and 0.079 mm² chip area including pads. The measured transmission losses across 81–86 GHz E-band frequency range are 3.6–5.2 dB for filter 1, 3.1–4.7 dB for filter 2 and 3.6–5 dB for filter 3 where rejection levels at the image band are >30 dB.

The previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit is implemented in this paper using a multi-stage positive polarity Reed–Muller representation with a composite field technique. The CSSAL and other conventional dual-rail adiabatic logics are evaluated from the view point of the transitional power fluctuation and the peak current traces in the 8-bit S-box in order to compare their resistance against side-channel attacks. A method to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block; thus, the CSSAL S-box circuit performs uniform peak current traces and it has significant power reduction, which is applicable for high security demand and low power devices, such as smart cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a 0.18-μm 1.8-V standard complementary metal–oxide semiconductor technology at an operating frequency band of 1.25 KHz–70 MHz.

In this paper, a coarse-fine time-to-digital converter (TDC) based on Vernier delay line (VDL) was proposed. A new digital circuit was developed for tree delay line and this method led to high resolution and low power consumption. The TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also took advantage of a VDL used in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffer of upper and lower chains. Then, with added extra chain in lower delay line, resolution can be controlled and area and power consumption was reduced. Measurement results of the TDC showed the resolution of 4.5 ps and output dynamic range of 32-bit and the differential non-linearity was always less the one least significant bits (1LSB), while the integral non-linearity showed the maximum of one least significant bits. This TDC achieved the consumption of 248.9 µW from 1.2 V supply.

H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual-standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 × 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 × 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 × 4320) frame in HEVC standard.