Novel closed form expressions for the error vector magnitude (EVM) are presented. The expressions combine the in-phase quadrature (IQ) amplitude and phase imbalances and the DC offsets along with the phase noise. Both the Gaussian and the Tikhonov probability density functions are utilised for the oscillator phase noise distribution. The explicit conditions when the EVM computations based on the Tikhonov distribution converge to a Gaussian based are investigated. Furthermore, the application of the proposed EVM expressions is demonstrated by including phase noise masks, providing a direct means to the phase locked loop/voltage controlled oscillator design parameters. The measurements are used to validate the proposed expressions.

A design of a 10-bit 27.8 kS/s 0.35 V ultra-low power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Nano-watt range power consumption is achieved thanks to the proposed segmented-capacitor array structure and ultra-low voltage design. To facilitate ultra-low voltage operation, a bulk-driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital-to-analogue converter (DAC) driving switch to relieve non-linearity. A new double-boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal-to-noise distortion ratio and 8.4-bit effective number of bits resulting in a figure-of-merit of 2.67 fJ/conversion-step.

This study presents a circuit theory approach for voltage stability assessment in an interconnected power network. Here, an interconnected IEEE 14-bus network has been reconfigured into 12-, 10- and 8-bus networks using graph theory. The line index indicator has been used for voltage stability assessment under normal and faulted conditions for the original (IEEE 14-bus) and the reconfigured (12-, 10- and 8-bus) networks. Genetic algorithm tool in MATLAB has been used to determine the optimal operating condition with best voltage stability for the original and the reconfigured networks. The results have shown that the voltage stability assessment under normal and faulted conditions can be effectively determined for the reconfigured networks compared with the original network.

An Ldi/dt effect model in the float ground driver system of plasma display panel (PDP) is established. First, considering key parasitic parameters, this study analyses the Ldi/dt effect appeared in power supply and ground pins because of switching transition of float-ground integrated circuits. Second, a set of differential equations model is described and validated with a good agreement with experiments. Based on the model, time-domain transient voltages and frequency spectra of the Ldi/dt effect are simulated and analysed with different values of parameter elements. Finally, subject to system demand limitation and the proposed model, the manual parameter design for reducing the Ldi/dt effect is presented, and a PDP system is used to validate the proposed approach.

In this paper, a novel amplifier linearisation technique based on the negative impedance compensation is presented. As demonstrated by using Volterra model, the proposed technique is suitable for linearising amplifiers with low open-loop gain, which is appropriate for RF/microwave applications. A single-chip CMOS amplifier has been designed using the proposed method, and the simulation results show that high gain accuracy (improved by 38%) and high linearity (IMD₃ improved by 14 dB, OIP₃ improved by 11 dB and adjacent channel power ratio (ACPR) improved by 44% for CDMA signal) can be achieved.

Recent high-speed digital-to-analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit-error rate testers at the required DACs rate. Among possible solutions, an inexpensive approach is the use of a multiplexer (MUX) with built-in memory to provide the required bit stream for one input bit of the DAC. This work presents a half-rate 32 GSps MUX with 1 kbit built-in memory as a part of an arbitrary test signal generator for a DAC. The proposed system can be used to test DACs developed for future OFDM optical communications. Here, a bipolar-CMOS (BiCMOS) 0.25 μm SiGe process is utilised. One challenge is to optimise the power dissipation of such an MUX which requires employing several techniques. At the system level, the conventional tree structure was avoided because of the high number of latches required to re-time the clock and data signals. At the highest rates, a multiphase-clock architecture was utilised which halves the number of latches compared with a tree structure. The phase margin of the multiphase-clock structure is enhanced in this work. At lower rates, a one-stage MUX architecture was used which also halves the number of latches. Additionally, the latency between the analogue–digital interface is discussed. All the implemented circuits including the biasing of the whole chip and its routing are presented. The design and optimisation of the clock driver for low-power functionality is discussed. Measurement results show proper operation at 32 GSps. The total power dissipation is 875 mW, which is the lowest power among the designs usable for DAC testing and at the same rate class.

Theoretical stability analysis of broadband cascode amplifiers at high frequencies is presented. The stability of the amplifier in the presence of parasitic inductive components is thoroughly investigated. It is shown that the stability can be improved by inserting a series resistance in the gate of common-gate device of the cascode amplifier. To ensure stability, the gate resistance should be selected within specific ranges that are derived analytically. Based on the insights provided by the analyses, several practical design guidelines are given to improve the stability of high-frequency broadband cascode amplifiers. Finally, the derived results are adopted in stabilisation of an X-band cascode amplifier implemented in a 0.18 μm complementary metal oxide semiconductor process.

Aggressive power management techniques, which combine hardware and software solutions, are fundamental for embedded computing platforms today, especially if they are battery operated. This paper proposes an adaptive low-level algorithm, which modulates the DC–DC converter activation for minimising quiescent current consumption. This algorithm allows a discontinuous usage of the DC–DC converter during the sleep time, without requiring modification in the user's main program, by powering the system solely with the internal DC–DC converter capacitor and without using any other additional capacitors as an energy buffer. The algorithm computes the maximum interval between consecutive wake-ups necessary for the capacitor recharging at run-time. Intervals are decided by taking into account both the global leakage and the temperature-dependent variations of the capacitor. The proposed solution significantly enhances the lifetime of applications with a low activity rate, such as wireless sensor networks, while still guaranteeing efficient power delivery for high-current demand intervals.

This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style circuits serves as a basis for the discussion. This basic SRAM design features a CML decoder, CML word line driver, bipolar sense amplifier for achieving high speed and CMOS 6T memory cells for high density. The BiCMOS technology is especially useful for realising ultra-high-speed SRAMs for low level cache memory in high-clock rate computer systems, but when reorganised can also be utilised in analogue-to-digital converter (ADC) systems to store digitalised data. Speed and power tradeoffs can be made using different bias strategies, CML logic levels and different generations of SiGe HBTs. A demonstrated 128 kb SRAM macro consumes 2.7 W at 4 GHz using a −3.4 and −1.5 V supply voltage for the bipolar and CMOS circuits, respectively, and has dimensions of 3.5 mm × 3.6 mm by using IBM 8HP SiGe technology, which provides an HBT with a f _T of 210 GHz. This macro can be integrated into large scale, ultra-wide bus SRAMs using heterogeneous silicon and 3D technology. Simulation indicates that with the next generation of SiGe HBTs, this SRAM macro can operate at 5 GHz, while consuming the same amount of power or alternatively consume 0.73 W, which is 73% less power consumption compared to 8HP, while operating with the same frequency of 4 GHz. Reorganising the memory for a 4 way-interleaved ADC, it can accept data written at 9.5 GS/s for 8HP designs, and 11.9 GS/s for 8XP designs.

Fractional motion estimation (ME) is commonly employed to improve motion compensation in video coding. However, the computational complexity is generally too high for real-time applications. This study proposes an efficient quarter-pixel estimation method implemented at both the algorithm and architecture levels. This approach to rapid estimation adopts a local full-search method to reduce the computational requirements while maintaining coding quality. We also developed a fast sub-pixel interpolation and parallel very large-scale integration (VLSI) architecture for quarter estimation to enhance processing speed. The overall VLSI architecture was developed for the estimation of fractional motion using a cell-based design. Three engines were implemented within a parallel structure: integer ME, sub-pixel interpolation and factional ME. The inclusion of pipeline scheduling enables the processing of one macro-block within 240 cycles. The gate count was ∼316 k and the maximum frequency was ∼160 MHz when implemented using Taiwan Semiconductor Manufacture Company 0.18 µm complementary metal oxide semiconductor process. The proposed chip achieved a throughput-rate of 662 k blocks per second.

A new complementary metal oxide semiconductor (CMOS) relaxation oscillator featuring with high linearity and low-jitter is presented in this study. The high linearity between the frequency and control current is achieved by adopting the floating capacitor and the independent charged and discharged loops. The low-jitter performance is gained because of that the voltage across the floating capacitor is larger than the conventional oscillator. The proposed circuit is compatible with standard CMOS process and one test-chip with typical frequency of 6.66 MHz was implemented in the 0.5 μm (bipolar–CMOS–double-diffused metaloxide semiconductor (DMOS)) (BCD) process. The measured results show that <0.86% non-linearity in the current–frequency transfer function from 1 to 6.66 MHz without trimming. The cycle-to-cycle jitter was <112 ppm.

Traditional noise reduction designs provide good performance but suffer from high complexity and long latency, which limits their application to hearing aids. Targeted for strict low-power and low-latency requirement of completely-in-the-canal type hearing aids, this study analyses and implements a previously proposed sample-based perceptual multiband spectral subtraction with a multiplication-based entropy voice activity detection. Simulation results reveal that the authors design can provide similar speech quality as others, but with lower computational complexity and simple control effort. The corresponding core-based architecture design further exploits processing characteristics of the proposed approach to reduce power consumption with a sign-magnitude and a preprocessed input data reuse scheme. Chip measurement shows that the design only consumes 83.7 µW at 0.6 V operation with 90 nm high threshold voltage (HVT) (high V_T ) standard cell library.

In an orthogonal frequency division multiplexing (OFDM)-based digital transmitter, the inverse fast Fourier transform (IFFT) processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the Cooley–Tukey-based decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed ‘pass-logic’. These replacements can be possible because the inputs are bitwise with binary-phase shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for 8 to 128 points (N) were implemented with multipliers and ‘pass-logics’. The performance improvements (PIs) of the proposed FFT/IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the total power by 6.5%. The same implementation on an ASIC, consumed 28% less power and 27% lesser gates. In 128-point implementation, these PIs are more than those of the 64-point, thus PI is in upward trend as N increases. A chip for FFT processing as per IEEE 802.11a specifications (64-point, 16-bit data) is designed with pass-logics, which uses 24 947 gates and consumes 6.45 mW at 1.8 V, 20 MHz in 0.18 µm 1P6M CMOS process.

In this study, a novel analytical method for new class of linear-phase two-dimensional (2D) finite impulse response (FIR) filter functions with full effect of Hilbert transformer in z ₁ and z ₂ domains generated by applying a new modified 2D Christoffel–Darboux formula for classical orthogonal Chebyshev polynomials of the first and the second kind is proposed. Fundamental research proposed in this study is also illustrated by examples of 2D FIR filter, Hilbert transformer and adequate comparison with new class of multiplierless linear-phase 2D FIR filter function given in the literature. For all 2D FIR filter functions, comparisons are made for the same values of free real parameters, and they show the improvement of the spike sharpness.

This study presents a three-mode controllable master-slave monostable multivibrator based on current-feedback operational amplifiers (CFOAs) for analogue signal-processing applications. The circuit is operated using a positive-edge triggering signal to generate the output pulses. The pulse width of the output signals can be adjusted by controlling the voltage, current or resistance to yield various circuit operating modes. This study also presents a three-mode controllable inverting and non-inverting operation master-slave monostable multivibrator to extend the application of the proposed circuit. In addition, the circuit operations, related governing equations, non-ideality analyses and experimental examples and results for the proposed monostable multivibrators are described. Commercially available CFOA integrated circuits (AD844ANs) and discrete passive components are used to construct the prototype circuits. The experimental results verified the validity of the proposed circuits.

In this study, a look up table (LUT) is developed to extract the intrinsic RF parameters of underlap DG MOSFET (UDG-MOSFET) including the non-quasi-static (NQS) effect. The LUT-based approach proposed; can accurately extract complex RF parameters of UDG-MOSFET under different bias conditions, necessary for RF circuit simulations by an interpolation algorithm. The RF parameters including intrinsic gate to drain capacitance (C _gd), gate to source capacitance (C _gs), gate to drain resistance (R _gd), gate to source resistance (R _gs), gate to source transconductance (g_m ), drain to source transconductance (g _ds), transport delay (τ_m ), capacitance because of DIBL (C _sdx) and inductance because of transport delay (L _sd), cut-off frequency (f _T) and maximum frequency of oscillation (f _max) are extracted using LUT approach. Parameters extracted using LUT are compared with simulated data, considering the NQS effect, and are found in good agreement. For RF circuit applications a low-noise amplifier is designed, with the UDG-MOSFET, operating at a tuned frequency of 10 GHz.

Frequency splitting patterns in low-order wireless power relay transfer systems are analysed by the coupled-mode theory. In addition to the V-type splitting pattern reported widely, two new patterns, I-type and W-type, are introduced. Specifically, it is found that a 0-relay system shows a V-type or I-type splitting; a symmetrical 1-relay system shows an I-type or W-type splitting; and a symmetrical 2-relay system usually shows a V-type or W-type splitting. The criteria for different frequency splitting patterns are given, and the theoretical results are validated finally by 1-relay and 2-relay wireless power transfer experimental systems.

The cascoded-compensation or ‘Cascomp’ amplifier offers excellent distortion reduction and thermal distortion rejection, but has not seen widespread use because of a limited gain and increased complexity compared with other topologies. The original theory showed that with the addition of an ideal error amplifier the circuit will completely compensate distortion for suitably chosen degeneration and bias values. This research presents a new, rigorous mathematical proof for conditions of compensation. The authors further develop the proof to include the non-idealities of the error amplifier. It is shown that there exists a second bias point, not exposed by the original analysis that offers improved gain while maintaining distortion cancellation. By reducing the error amplifier degeneration resistance, one can increase a Cascomp circuit's overall gain by several dB while maintaining theoretically perfect distortion compensation. A robust bias point is proposed, which takes the advantage of this new theory by optimising circuit values resulting in a comparatively broader and deeper third-order distortion null. The proposed theory is confirmed with simulation and measurement that show agreement within the bounds of process and component error limits.

A 600 V high-voltage gate drive IC (HVIC) using a novel robust isolation structure and a new delay circuit with low-temperature coefficient is proposed in this study. The novel isolation structure features with n⁻-well islands alternatively arranged in the p-well region and its breakdown voltage is improved by about 7% (from 690 to 740 V) compared with the conventional isolation because of that the electrical field crowed in the p-well corner is ameliorated. The presented delay circuit used in the gate drive IC is composed of a temperature-insensitive ramp generator and a comparator. The typical turn-on/-off propagation delay time of the HVIC is 95 ns/85 ns and its maximum temperature coefficient is only 0.065 ns/°C.

A 37 dBm power amplifier (PA) is designed on a 0.25 µm optical T-gate pseudomorphic high electron mobility transistor (pHEMT) technology. The design of this two-stage PA along with a step-by-step design procedure is presented in this paper. This methodology can be used for design of PA in different technologies and frequencies. The PA delivers 5 W output power over the frequency band of 13–19 GHz. It shows average power-added efficiency of 37% and large signal gain of 15 dB in measurements which is consistent with simulation results. The output power and efficiency of the realised amplifier reach maximums of 37.6 dBm and 45%, respectively. Considering output power, bandwidth, chip area and efficiency, this PA exhibits competitive performance compared to the reported PAs.