This study focuses on the design of high-loop-delay modulators for parallel sigma–delta conversion. Parallel converters, allowing a global low oversampling ratio, consist of several bandpass modulators with adjacent central frequencies. To ensure the global performance, the noise transfer function (NTF) of each modulator must be adjusted regarding its central frequency. In this thematic a new topology of sixth-order modulators based on weighted-feedforward techniques is developed. This topology offers an adequate control of the NTF at each central frequency by simple means. Additive signal paths are moreover proposed to obtain an auto-filtering signal transfer function. An optimisation method is also developed to calculate the optimised coefficients of the modulators at different central frequencies. The main concerns are improving the stability and reducing the sensitivity of the continuous-time circuit to analogue imperfections. This is essential for parallel conversion since, in each channel, the modulator works at a central frequency which differs from the fourth of the sampling frequency. The performance of the optimised modulator is compared with its discrete-time counterpart with good argument.

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm².

In this paper, we have proposed a novel scheduling scheme for generating continuous input-blocks for the succeeding processing units of parallel structure to achieve 100% hardware utilisation efficiency (HUE) without block folding. Based on the proposed scheme, we have derived a parallel and pipeline structure for multilevel lifting two-dimensional discrete wavelet transform (DWT). The proposed structure involves regular data-flow and does not require frame-buffer, and calculates DWT levels concurrently. A theoretical comparison shows that the proposed structure for J = 2 involves 1.25 times more multipliers and adders, 2N more registers than those of existing folded block-based structure and offers 1.25 times higher throughput, where N is the input-image width. Compared with similar existing parallel structure, the proposed structure requires the same number of multipliers and adders, 2.125N less registers and offers the same throughput rate. Application specific integrated circuit synthesis result shows that the core of the proposed structure for 2-level DWT and image size (512 × 512) involves 41% less area-delay-product and 36% less energy-per-image than those of similar existing parallel structure.

A new method for the synthesis of active RC circuits employing multiple output current controlled conveyors (Mo-CCCIIs) is presented here. A new graph is proposed for Mo-CCCII and the application of this graph in active filter design is studied. The obtained active filter uses Mo-CCCIIs as active devices and only capacitors as passive elements without the need of passive resistors. To generalise the proposed method, an algorithm is presented, which converts the loop–cut-set matrices of the passive LC filter prototypes to the proper matrices for Mo-CCCII-based active filters. The new matrices characterise the connections of the equivalent Mo-CCCII-based active filter. The presented algorithm is programmed in MATLAB, so the matrix manipulation is done very quickly. Also, Hspice simulation result of the synthesised active filter is given to confirm the viability of this approach.

The last main stage in an automatic number plate recognition system (ANPRs) is optical character recognition (OCR), where the number plate characters on the number plate image are converted into encoded texts. In this study, an artificial neural network-based OCR algorithm for ANPR application and its efficient architecture are presented. The proposed architecture has been successfully implemented and tested using the Mentor Graphics RC240 field programmable gate arrays (FPGA) development board equipped with a 4M Gates Xilinx Virtex-4 LX40. A database of 3570 UK binary character images have been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can meet the real-time requirement of an ANPR system and can process a character image in 0.7 ms with 97.3% successful character recognition rate and consumes only 23% of the available area in the used FPGA.

In this study, electrical behaviour of dual-gate (DG) and single-gate (SG) organic thin film transistors (OTFTs) is investigated using Atlas two-dimensional (2D) numerical device simulation. Compared with the SG, DG organic transistor shows improved performance because of the presence of two channels formed in DG device by charge carrier modulation. Furthermore, this study introduces all-p organic inverter circuits with diode-load and zero-V _gs-load logic configurations using SG and DG structures. Static and dynamic behaviour of all-p organic inverter circuits is compared with addressing the effect of both the devices. A maximum voltage gain (A_V ) of 16 is obtained in zero-V _gs-load logic using DG-OTFT, whereas SG-OTFT configuration produces a maximum A_V of about 6.27. Significant improvements in propagation delay of 66% for diode-load and 53% for zero-V _gs-load logic using DG-OTFT are obtained as compared with SG-OTFT.

A new solution for a low-voltage bulk-driven CMOS operational amplifier is presented in this study. The amplifier is designed using 50 nm process parameters and optimised for 0.5 V supply voltage. The circuit consumes 100 μW, performing 74 dB open-loop gain, 59 nV/Hz^1/2 input referred noise at 1 MHz and 4.8 MHz gain bandwidth product (GBP) for 20 pF load capacitance.

This work presents an electrically actuated, aluminium nitride based, piezoelectric tuning fork designed at the micro-scale for selective modal actuation. This well known resonator, whose advantages have been widely studied and exploited in the milli-scale, has been implemented and studied in the micro-scale, showing promising results. A complete optical and electrical characterisation of the device has been carried out, in which various out-of-plane and in-plane vibration modes have been analysed. Its performance has been studied in vacuum, air and water. High-quality factors (Qs) up to 72 in water and up to 5166 in air have been measured for the in-plane anti-phase mode. This Q-factor is higher than any other value published with the in-plane piezoelectric micro-cantilevers in air. Sensitivity as mass sensor and minimum detectable mass has also been estimated in air. Sensitivity values almost three orders of magnitude higher than millimetric commercial tuning forks have been achieved. Easy integration, simple and selective actuation and a Q make this kind of resonator an attractive alternative in a wide range of applications.

A dual-band quadrature voltage-controlled oscillator (QVCO) with high figure-of-merits (FOMs) and cost-area efficiency is presented by integrating with differential inner-diamond-structure switchable inductors which have improved performances. This proposed QVCO is fabricated in a 0.18-μm complementary metal-oxide semiconductor process with an active-region area of 0.61 mm². The QVCO core totally consumes 6.8 mA from 1.8 V supply voltage. The frequency tuning ranges are 120 MHz (from 3.18 to 3.3 GHz) for the low-band and 500 MHz (from 6.94 to 7.44 GHz) for the high-band, while the tuning voltage rises from 0 to 1.8 V. The best phase noises with an offset frequency of 1 MHz from the oscillation frequency in the low- and high-bands are −121.9 and −117.5 dBc/Hz, respectively. The measured phase errors in both high-band and low-band are less than 1°. The calculated FOMs, no matter the switch is off or on, are better than −180 dBc/Hz.