This work introduces a fundamental methodology enabling to identify the elementary negative group delay (NGD) topologies using transistors. These circuits are particularly beneficial compared to the other existing NGD topologies, with its flexibility to operate in ultra wideband (UWB), to compensate losses and potentially integrable. The basic families of NGD topologies obtained from the association of passive and active four-port networks are presented. The NGD existence condition is given. Based on this condition, the simplest NGD active cells are identified. After the analysis of passive networks formed by R, L and C components, first-order transfer functions of innovative elementary NGD cells are established. Then, similar to the classical circuits as the filters and amplifiers, synthesis relations for the design of integrable NGD topology with no self-element are introduced. To illustrate the relevance of the theoretic concept, a proof of concept was proposed. Finally, discussions on the applications of NGD circuits are offered in the conclusion.

This study proposes a new SPICE model for thermoelectrical modules (TEMs) that takes into account the internal parameters variation with temperature. Prior work considers constant values for the three factors that determine the figure of merit: Z = ((σS ²)/k), that is the electrical conductivity, the Seebeck coefficient and the thermal conductivity. This leads to large errors in simulation because the parameters vary strongly with temperature. The new model also employs the parasitic elements that appear in a TEM and not discussed in prior works. The proposed model uses experimental data from several TEMs of different manufacturers. The thermoelectrical model of the entire system will be afterwards validated through experiment. A thermoelectric energy-harvesting system is proposed and simulated based on the improved TEMs model. The results show that our model can be used for more accurate simulations when designing TEM-based applications.

In this study, a low-power, high-speed, layout-efficient 8b × 8b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 µm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

This study proposes passive voltage shifters that shift the median value of an analogue signal by either a multiple or a fraction of the amplitude of the input signal in positive or negative directions. The proposed voltage shifters are powered by the input signal, making them particularly attractive for applications such as implantable devices where power is critical. The primitive configuration of the voltage shifters also makes them well suited for high-frequency applications. A detailed mathematical treatment that quantifies the principle of the voltage shifters is presented. Factors affecting the performance of the proposed voltage shifters are examined in detail.

A family of multiplierless transforms is presented that approximate the eight-point type-II discrete cosine transform (DCT) as accurately as the state-of-the-art scaled DCT schemes, but having 14–17% shorter critical paths (1/6 or 1/7 less adders). Compared to the existing solutions that use the coordinate rotation digital computer (CORDIC) algorithm, the advantage of higher throughput is accompanied by saving additions. Only some lifting-based BinDCT schemes require less adders in total, in spite of longer critical paths. The transforms have been derived from the fast Loeffler's algorithm by replacing the rotation stage with unfolded CORDIC iterations, which have been arranged so that two rotation approximations use the same scaling. This is equivalent to imposing structural orthogonality (losslessness) on a system, from which the scaling can then be extracted so as to shorten the critical path. Supporting ideas are a notation for more conveniently describing CORDIC circuits, and an angle conversion that allows rotations to be approximated using an extended set of CORDIC circuits. The research results have been validated by field programmable gate array-based hardware design experiments and by usability tests based on a software JPEG codec.

This study presents a 1–5.6 Gb/s CMOS clock and data recovery (CDR) integrated circuit (IC) implemented in a 0.13 μm CMOS process. The CDR uses a half-rate linear phase detector (PD) of which static phase offset is compensated by an additional binary PD and a digital charge pump (CP) calibration block. During initialisation, the static phase offset is detected by the binary PD and the CP current is controlled accordingly to compensate the static phase offset. Also, the architecture of this CDR IC is designed for a clock embedded serial data interface which transfers CDR training clock patterns before normal random data signals. The implemented IC consumes 16–22 mA from a 1.2 V core supply for data rates of 1–5.6 Gb/s and 20 mA from a 3.3 V I/O supply for two preamplifiers and low-voltage differential signalling drivers. When the 2³¹–1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10^–12 and the jitter tolerance is 0.3UI_pp. The recovered clock jitter is 21.6 and 4.2 ps_rms for 1 and 5.6 Gb/s data rates, respectively.

This study presents a new equivalent circuit modelling methodology for various-type spiral resonators in printed circuit board environment. The N-turn spiral resonator can be decomposed into an N Π-equivalent circuit model, and each Π-model is comprised of a series inductance, parallel capacitance, two shunt capacitors and the resistances of the conductor and dielectric. Both the inductance and capacitance of the equivalent circuit are calculated by the proposed formulas, which are based on the electromagnetic theory. It has been demonstrated that the proposed equivalent circuit model of the spiral resonator is well matched in S-parameters, Q-factor and inductance values as well as in self-resonance frequency values within 8% tolerance with measurement and full-wave electromagnetic field solver.