This study presents an 8-bit asynchronous reference-free successive-approximation-register analogue-to-digital converter (ADC). A novel charge recycling method is proposed to decrease the power consumption by switching the two separated capacitor arrays alternatively in the first four phases of one conversion. The last four phases stick to the conventional method. According to the calculation and the MATLAB simulation, 67% energy reduction is obtained. The four largest capacitors in the main array and the two capacitors in the helper array are broken into halves to generate the positive and negative comparison references, respectively. Combining an aggressive unit capacitance layout scheme and the proposed capacitor layout distribution, the matching performance, the geometric shape and the wiring parasitics are improved. The over-sampled system clock is not required with the asynchronous timing control of the successive comparisons. The reference-free configuration utilises power supply and ground instead of two dedicated buffered voltage references. The prototype ADC is fabricated in semiconductor manufacturing international corporation (SMIC) 0.18 μm complementary metal oxide semiconductor (CMOS) process. At 12 MS/s sampling rate and 1.1 V power supply, it consumes 130 μW and achieves a signal-to-noise-and-distortion-ratio of 47.4 dB, resulting in a figure-of-merit of 58.4 fJ/conversion-step and an active area of 0.1 mm².

The performance characterisation of a microwave transistor is carried out rigorously based on the linear circuit and noise theories, subject to the maximum output power and the predetermined input termination. For this purpose, the transducer gain G _T is maximised analytically with respect to the input termination Z _S for the output port matched, provided that Z _S meets the noise figure requirement F _req ≥ F _min remaining within the unconditionally stable working area (USWA). Analysis is made in the z-parameter domain which facilitates a single unique crescent conditional stability configuration to replace the eight different, rather complicated stability configurations in the S-parameter domain. Finally, the compromise relations between the gain, noise figure for the output port matched are obtained with typical design configurations depending on the operation conditions of a selected high technology transistor. Incompatible noise and gain requirements can also be observed in their design configurations. Furthermore the cross-relations among the bias condition (V _DS, I _DS) and ingredients of the performance {F _req ≥ F _min, V _out = 1, G _T ≤ G _Tmax} triplets and together with their terminations {Z _S, Z _L = Z*_out(Z _S)} can be formed basis for “Performance Data Sheets” of microwave transistors to be employed for the amplifier designs of maximum output power and low noise.

In this study, low-power and low-component count grounded and floating current-controlled tunable resistors are proposed. The validity of the proposed resistor circuits is demonstrated in two applications, second-order band-pass filter and negative inductor simulator circuit. To carry out the performance of the circuits, all the designed circuits are simulated through SPICE program by using real transistor models. Also, experimental results are included to confirm the theory. It is important to note that all the introduced circuit parameters and resistor values can be changed electronically by adjusting the values of dc control current sources only. Approximately four decades tunability range (from 34 Ω to 285 kΩ) and about 10 MHz bandwidth for the tunable resistors are achieved. In this tunability range, linear relationships between terminal currents and voltages are successfully obtained.

This study describes a 0.38 V digitally controlled low-dropout (LDO) voltage regulator enabling dynamic voltage scaling (DVS) for near/sub-threshold applications. For operating at an ultra-low supply voltage, analogue components are replaced in conventional LDOs with digital counterparts. Especially, a digital reference control that is based on a replica circuit is proposed to improve power supply noise rejection and line regulation of the LDO. The proposed LDO has been designed in a 90 nm regular V _T complementary metal oxide semiconductor technology. The LDO can regulate the output voltage from 0.12 to 0.32 V with a supply voltage of 0.38 V. Furthermore, it reaches the current efficiency of 99.3% and the power efficiency of 83.6%, respectively, at a load current of 1 mA. The digitally controllable DVS with 3 mV resolution is achieved.

An analytical model for current (I)–voltage (V) characteristics of a short-channel ion-implanted GaAs MESFET has been presented for dark and illuminated conditions. For the sake of simplicity, the non-analytic (i.e. non-integral) Gaussian doping function commonly considered for the channel doping of an ion-implanted GaAs metal semiconductor field effect transistor (MESFET) has been replaced by an analytic Gaussian-like doping profile in the vertical direction. The device uses an indium–tin oxide-based Schottky gate through which an optical radiation of 0.87 μm wavelength is coupled from an external source into the device to modulate the I–V characteristics of the short-gate length GaAs MESFET. The coupled light generates electron–hole pairs in the active channel region below the gate and develops a photovoltage across the Schottky gate–channel junction and modulates the device characteristics. This study also includes the modelling of this photovoltaic effect by taking the short-gate length effects into consideration. The developed model includes the effects of doping profile and device parameters on the drain current of the short-channel ion-implanted GaAs MESFETs under dark and illuminated conditions of operations. The accuracy of the proposed model is extensively verified by comparing the theoretically predicted results with numerical simulation data obtained by using the commercially available ATLAS^TM device simulation software.