Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 6, Issue 6, November 2012
Volumes & issues:
Volume 6, Issue 6
November 2012
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- Author(s): K.-Y. Park ; W.-S. Oh ; Y.-S. Lee ; W.-Y. Choi
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 375 –385
- DOI: 10.1049/iet-cds.2012.0029
- Type: Article
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p.
375
–385
(11)
We report a fully integrated serial-link receiver with optical interface fabricated with a 0.18 µm complementary metal oxide semiconductor technology for long-haul display interconnects. The receiver includes a trans-impedance amplifier, a limiting amplifier, a clock and data recovery circuit, 1:64 de-multiplexer and a built-in error checker. The receiver produces 64-bit wide electrical signals from photodetector output signals produced by 5.28, 5.6 or 6.25 Gb/s optical signals delivered through up to 700-m multi-mode fibre. It can support serialised data for Ultra eXtended Graphics Array (UXGA), 1080 p and Wide Ultra eXtended Graphics Array (WUXGA). The receiver core occupies 0.59 mm2 with 42.4 mW power dissipation at 6.25 Gb/s bit rate from a 1.8 V supply. - Author(s): G. Scandurra ; G. Cannatà ; C. Ciofi
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 386 –396
- DOI: 10.1049/iet-cds.2012.0140
- Type: Article
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p.
386
–396
(11)
It has recently been proposed by a few authors that the trigonometric Pythagorean identity can be used for the implementation of precision full-wave rectifiers for sinusoidal signals with advantages with respect to diode-based rectifiers for amplitudes in the hundreds of mV range. The approaches proposed so far require a 90° phase shifter and this results in the obvious limitation that the input signal frequency must be known prior to amplitude measurement. In this study, the authors propose a new precision full-wave rectifier, capable of overcoming this limitation. Starting from the sinusoidal input, a squared co-sinusoidal signal is obtained in a wide frequency range by multiplying the output signals of an integrator and of a differentiator. The signal thus obtained is added to the input signal squared, and a square root extractor is employed for obtaining a DC signal proportional to the amplitude of the input signal. A prototype capable of operating within a two decades frequency range across 3200 Hz has been realised and tested with an accuracy better than 2% and a residual ripple of less than 0.3% for input amplitudes larger than 100 mV. A configuration capable of operating in the MHz frequency range is also proposed. - Author(s): I. Kianpour ; M. Baghaei-Nejad ; L.-R. Zheng
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 397 –405
- DOI: 10.1049/iet-cds.2011.0238
- Type: Article
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p.
397
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In this study an ultra-low-power successive approximation register (SAR) analogue-to-digital converter (ADC) for radio frequency identification (RFID) applications is presented. Several techniques are used to further reduce power consumption and relatively elevate the speed of the conventional SAR ADC. These techniques include a low-power comparator with no static current, a dual-stage (resistor-string/capacitive dividing) architecture as digital-to-analogue converter (DAC), and utilising low-power design with the aid of low supply voltages: 0.7 V for DAC, and 0.5 V for SAR block and pulse generator circuitry (PGC). In the DAC architecture fine search will be performed by only two C and 15C capacitors which reduce the silicon area significantly. The circuit designed in 0.18 µm complementary metal-oxide-semiconductor (CMOS), technology and post-layout simulations show that the 8-bit core ADC consumes almost 78.4 nW at 17.8 kS/s speed whereas the PGC block consumes 84.1 nW. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison to its charge redistribution counterparts. - Author(s): M.A. Arafat and A.B.M. Harun-ur-Rashid
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 406 –412
- DOI: 10.1049/iet-cds.2012.0057
- Type: Article
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p.
406
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In this study, a novel low-power high data rate ultra-wideband (UWB) pulse generator circuit is presented, which can be fully integrated in complementary metal oxide semiconductor (CMOS) process. The basic part of the circuit generates a UWB Gaussian monocycle pulse using the triangular pulse generation technique. A new bipolar phase shift keying pulse modulator is designed to control the polarity of the output pulses. The design includes additional functionality to make the pulse generator also applicable for transmitted reference (TR) signalling system. The circuit can generate pulses at a maximum rate of 7 giga pulse per second (Gpps) without TR pulse (TRP) and 3.5 Gpps with TRP. The generated pulses are symmetrical, each having a width of 142 ps and a peak-to-peak swing of 500 mV. The −3 dB bandwidth of the pulse spectrum is 9 GHz. The pulse generator consumes only 1.13 pJ per pulse from 1.2 V supply. The circuit is designed and simulated in 90 nm CMOS technology. - Author(s): J.A.R. Azevedo and F.E.S. Santos
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 413 –420
- DOI: 10.1049/iet-cds.2011.0287
- Type: Article
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p.
413
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It is well-known that wireless sensor networks (WSNs) promise to revolutionise the way the authors can interact with the physical world. However, the deployment of these systems in practical environments is very limited because of power constraints. Systems based on solar, vibrational and thermal energy are the most used in WSN applications and only a few studies consider the wind for energy harvesting. Another important source of energy is the water flow. In the context of the WSN, it was found that there are practically no systems using such source. The purpose of this study is to evaluate the use of small-scale wind and hydro generators for energy harvesting to power wireless sensor nodes. For this purpose, the power coefficients and the output power of several horizontal-axis and Savonius wind turbines were determined. Systems based on Pelton and propeller turbines were constructed to evaluate the effect of some parameters in small-scale power generation. - Author(s): H. Alzaher ; O. Alees ; N. Tasadduq
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 421 –428
- DOI: 10.1049/iet-cds.2012.0086
- Type: Article
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p.
421
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A novel multi-output current amplifier exhibiting independent electronically controllable gains is proposed. The new device provides a cost-efficient and low-power solution to filter designs. While multi-output devices are often employed to reduce active components within the filters, the proposed device conserves the independent tuning characteristics. Current-mode two-integrator-loop filter topologies are considered as the demonstrating examples. The experimental results obtained from a 0.18 µm complementary metal oxide semiconductor (CMOS) process are provided. - Author(s): B.P. Das and H. Onodera
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 429 –436
- DOI: 10.1049/iet-cds.2012.0012
- Type: Article
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429
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Today's multi-million digital integrated circuit design highly depends on the quality of the standard cell library. In this study, an all-digital reconfigurable-array-based test structure is presented to test the quality (i.e. functionality and performance) of all types of logic gates in the standard cell library using the reconfigurable array of gate delay measurement cell. The gate delay is estimated using the least squares method with measured reconfigurable ring oscillator's (RO) period/frequency. As the least squares method averages out the random noise in the measured RO period, measured gate delay is estimated accurately. The reconfigurable-array structure can easily isolate a faulty standard cell from a non-faulty standard cell. The test structure is area efficient with a saving of 1.6× and 2× area compared with the normal RO-based delay measurement in 180 nm and 65 nm technology node, respectively. A subset of standard cells is tested using this reconfigurable-array structure. A test chip has been fabricated in an industrial 180 nm technology node to study the feasibility of the approach. The measured results from 20 chips are reported to show the amount of within-die and die-to-die variation. - Author(s): C. Najoua ; B. Mohamed ; B.M. Hedi
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 437 –446
- DOI: 10.1049/iet-cds.2011.0367
- Type: Article
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437
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In this study, the authors present field-programmable gate array dynamic power models for basic operators at the architectural level. Other models are developed for operator groups arranged in parallel or in series in the architecture. The operator's characterisation models depend on the frequency variation, the activity rate and precision in the presence of autocorrelation, taking into account the interconnections between operators. The authors have validated their approach by the Euclidean distance and finite-impulse response filter applications while using the operator models in a first step and the IPs models in a second step. The estimation results show that the estimate is even closer to the real value when IPs mathematical models are used, and the experimental ones show a higher average accuracy and the maximum average error reached is equal to 3.7%. The power models are verified by an on-board measurement based on a Virtex2Pro field-programmable gate array real environment and is ready for integration with high-level power optimisation techniques. - Author(s): S. Askari and M. Nourani
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 447 –456
- DOI: 10.1049/iet-cds.2012.0053
- Type: Article
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447
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N-tuple modular redundancy techniques have been widely used to improve the reliability of digital circuits. Unfortunately, an equivalent technique has been rarely used for analogue and mixed-signal systems. In this study, propose a redundancy-based fault-tolerant methodology is proposed to design highly reliable analogue and mixed-signal circuits. The key contribution of the proposed work is: (a) systematic sensitivity analysis to identify critical nodes in a circuit and (b) a design methodology for improving the reliability of analogue and mixed-signal circuits using an innovative mean voter. The mean voter is a low-power, small area, very high bandwidth and linearly scalable unit; and it works for both odd and even redundancy factors. For the proof of concept, the authors designed two analogue-to-digital converters and an analogue filter, which are used in mixed-signal applications. Experimental results are reported to verify the concept and measure the system's reliability when failures, such as single upset transient faults, occur. - Author(s): L. Wen ; Z. Li ; Y. Li
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 457 –464
- DOI: 10.1049/iet-cds.2012.0002
- Type: Article
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p.
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Dynamic circuits are extensively employed in very-large-scale integration chips because of their high performance. Unfortunately, they are more susceptible to noise than static complementary metal oxide semiconductor circuits. With the continuous down-scaling of process technology and the supply voltage, improved noise immunity in dynamic circuits is essential. In this study, two new schemes are proposed to enhance the noise tolerance of dynamic address decoders, and their performance, noise tolerance and power consumption are compared with those of a conventional dynamic decoding circuit and a previous scheme. A dynamic 4–16 decoder employing the proposed delay technique exhibits 131.5 and 2.6% improvements in noise tolerance and performance, respectively, whereas a 4–16 decoder exploiting the proposed mirror scheme achieves 291.2 and 25.2% improvements; both used 65 nm process technology. Moreover, the proposed techniques are more resistant to process variations and more tolerant of a lower power supply. - Author(s): S. Liang and W. Redman-White
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 6, p. 465 –472
- DOI: 10.1049/iet-cds.2012.0014
- Type: Article
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p.
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An integrated frequency synthesiser is designed and implemented in standard 130 nm complementary metal-oxide semiconductor (CMOS) technology for spectrum monitoring receiver function needed in an associated cognitive radio system. This function demands very wide continuous tuning range albeit with only moderate phase noise performance, although low-power consumption and small die area are high priorities. To meet these unusual specifications, a ring oscillator is used as the frequency source, and a novel high-speed low-power integer-N programmable divider is developed to achieve the tuning range. Using a 25 MHz reference frequency, the ring oscillator-based synthesiser tunes continuously from 5 to 7.3 GHz with 100 MHz steps, maintaining the measured phase noise and reference spur levels below −80.5 dBc/Hz at any frequency offset between 100 kHz and 100 MHz for all output frequencies. The power consumption of the complete frequency synthesiser (excluding the output buffer and the reference crystal oscillator) is 9.98 mW from a 1.2 V supply.
Fully integrated serial-link receiver with optical interface for long-haul display interconnects
Wide bandwidth Pythagorean rectifier
78 nW ultra-low-power 17 kS/s two-step-successive approximation register analogue-to-digital converter for RFID and sensing applications
A novel 7 Gbps low-power CMOS ultra-wideband pulse generator
Energy harvesting from wind and water for autonomous wireless sensor nodes
Programmable multi-gain current amplifier
Area-efficient reconfigurable-array-based oscillator for standard cell characterisation
Power estimation model based on grouping components in field-programmable gate array circuit
Design methodology for mitigating transient errors in analogue and mixed-signal circuits
High-performance dynamic circuit techniques with improved noise immunity for address decoders
Integrated CMOS wide tuning range integer-N frequency synthesiser for spectrum monitoring functions in cognitive radio systems
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