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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 6, Issue 5, September 2012

Volume 6, Issue 5

September 2012

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    • Editorial: Thermal, power and timing modeling, design and simulation
      Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution
      Low-power processor architecture exploration for online biomedical signal analysis
      Using unified power format standard concepts for power-aware design and verification of systems-on-chip at transaction level
      Worst-case temperature analysis for different resource models
      Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip
      Power profiling-guided floorplanner for 3D multi-processor systems-on-chip
      Iterative timing analysis based on nonlinear and interdependent flipflop modelling
      Integrator clamping for asynchronous sigma-delta modulator central frequency increment
      Secure D flip-flop against side channel attacks
      Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime
      On-chip process variation-tracking through an all-digital monitoring architecture

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