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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 6, Issue 4, July 2012

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Volume 6, Issue 4

July 2012

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    • Closed-form model for the open circuit voltage of solar cells with shunt resistance, bias-dependent photocurrent and double exponential terms
      • Author(s): H. Saleem  and  S. Karmalkar
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 211 –217
      • DOI:  10.1049/iet-cds.2011.0173
      • Type: Article
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      • p. 211 –217 (7)
        The parasitic shunt resistance, bias dependence of the photocurrent and phenomena causing a second exponential term in the current density (J)–voltage (V) equation reduce the open circuit voltage, Voc, of illuminated solar cells below the ideal value predicted by the J–V equation having only a single exponential term. This study reports an approximate closed-from solution of the transcendental Voc equation which directly reflects these losses. The solution estimates Voc as a weighted parallel combination of the limiting Voc values corresponding to the domination of one of the several terms of the Voc equation. The solution allows quick design calculation of the Voc of a wide variety of cells in terms of all physical parameters, and provides insight into the influence of losses owing to various factors.
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      Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients
      • Author(s): S.S. Rathod ; A.K. Saxena ; S. Dasgupta
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 218 –226
      • DOI:  10.1049/iet-cds.2011.0253
      • Type: Article
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      • p. 218 –226 (9)
        In this study, the authors evaluate different schemes of address decoders based on bulk, single gate (SG) silicon-on-insulator (SOI) and double gate (DG) FinFET technology. Schemes differ in terms of back gate connections, and swing on the enable and address lines. The analysis for delay, power dissipation and critical charge has been carried out. Radiation induced single event transients and multiple bit upsets in address decoder have been studied. For radiation hardened applications, tied gate configuration has been found to be good choice over bulk, SG-SOI and independent gate configurations. The effect of process parameter variations on different schemes has been studied. HSPICE simulations have been performed with 45 nm bulk, SG-SOI and DG-FinFET predictive technology models.
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      Power-efficient decoder implementation based on state transparent convolutional codes
      • Author(s): Y.-H. Shiau ; H.-Y. Yang ; P.-Y. Chen ; S.-G. Huang
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 227 –234
      • DOI:  10.1049/iet-cds.2011.0055
      • Type: Article
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      • p. 227 –234 (8)
        In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.
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      Heuristic finite-impulse-response filter design for cascaded ΣΔ modulators with finite amplifier gain
      • Author(s): Y.-S. Chou ; C.-C. Lin ; H.-L. Chen ; J.-S. Chiang
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 235 –245
      • DOI:  10.1049/iet-cds.2011.0177
      • Type: Article
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      • p. 235 –245 (11)
        This study addresses a new digital calibration filter design for cascaded ΣΔ modulators with finite amplifier gain. A recent approach based on the H-infinity loop shaping method to this problem has the merit of obviating the use of an estimation or adaptive digital correction scheme, which thus reduces the complexity of circuit implementation. For the approach to be successful, it is critical to find an appropriate weighting function so as to make the gain responses of the uncertain noise transfer function (NTF) in a proper shape for improving signal-to-noise ratio (SNR). However, the search of such a weighting function is difficult in general. Moreover, the introduced weighting function increases filter order and hence circuit complexity. To circumvent this difficulty and the inherited drawbacks, this study presents a new noise shaping method for the problem. Considering that it is hard to decide the optimal shape of the uncertain NTF a priori, the authors propose a dual-band design to achieve the shape adjustment task. In particular, the range of lower frequency band is determined by SNR performance evaluation rather than being arbitrarily given a priori. This step is crucial and increases the chance of finding a better filter.
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      Design of rectifier diode temperature compensation circuit in flyback converter
      • Author(s): L.F. Shi ; Y.J. Chang ; H.S. He ; H.Y. Nie ; Y.R. Zhao
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 246 –251
      • DOI:  10.1049/iet-cds.2011.0254
      • Type: Article
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      • p. 246 –251 (6)
        A rectifier diode temperature compensation circuit is presented for primary-side controlled flyback converter. By compensating the variation of secondary-side rectifier diode forward voltage with temperature, the error rate of output voltage in flyback converter will be effectively improved at high temperature. The design of the circuit is based on the negative temperature characteristics of the base-emitter voltage VBE of bipolar transistors. Besides, the circuit can also provide over-temperature protection. Results of simulation based on 0.5 µm bipolar complementary metal oxide semi-conductor process show that the compensation voltage is 0.1 V at 125°C and 0 V at 25°C. The maximum output voltage error rate of flyback converter with compensation is from 3.8 to 0.6% under the temperature between 25 and 125°C. The thermal shutdown threshold is 140°C, and the over-temperature protection hysteresis threshold is 110°C.
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      Efficient inclusive analytical model for delay estimation of multi-walled carbon nanotube interconnects
      • Author(s): M. Gholipour  and  N. Masoumi
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 252 –259
      • DOI:  10.1049/iet-cds.2011.0283
      • Type: Article
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      • p. 252 –259 (8)
        Multi-walled carbon nanotubes (MWCNTs) have attracted much attention as very large scale integration (VLSI) chip interconnects, because of their high-current densities and excellent thermal and mechanical properties. This study investigates different aspects of the use of MWCNTs as chip routing wires to seek modern technologies for high-performance interconnects. Mathematical analyses, and simulations were made for MWCNT and Cu at global, intermediate and local interconnect levels. The authors propose a semi-analytical delay estimation model along with an equivalent RC model for MWCNT global interconnects. The results obtained from these models show good conformance with the simulation results. The proposed compact semi-analytical model can be used to perform fast analysis of MWCNT global interconnects, including delay, buffer insertion and crosstalk. The authors exploited their model to investigate the impact of buffer insertion on MWCNT interconnect delay. The optimal number of required buffers is estimated, as it minimises the MWCNT propagation delay. Analytical and simulation results show that the MWCNT interconnects require lower number of buffers compared to Cu wires.
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      Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield
      • Author(s): H. Makino ; S. Nakata ; H. Suzuki ; S. Mutoh ; M. Miyama ; T. Yoshimura ; S. Iwade ; Y. Matsuda
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 4, p. 260 –270
      • DOI:  10.1049/iet-cds.2012.0090
      • Type: Article
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      • p. 260 –270 (11)
        This study describes a method to easily predict the write yield of a static random access memory (SRAM) memory cell. The differential coefficient of the combined word line margin (CWLM) for the threshold voltage (Vth) is analysed using the simple Schockley's transistor model. The analysis shows the good linearity comes from keeping the access transistor operating in the saturation mode for a wide range of Vth's. The Monte Carlo simulation demonstrates that the CWLM obeys the normal distribution. The mean and the variance of the CWLM are almost constant for sample numbers ranging from 100 to 100 000. The estimated write failure probability are almost uniform within a factor of 1.7 for the number of samples more than 300, which allows us to evaluate SRAM with a small number of measurements. The predicted distribution using the differential coefficient calculated by the SPICE simulation also matches the Monte Carlo results. The estimated write failure probability agrees with the Monte Carlo results within a factor of 2.0, which is acceptable for SRAM redundancy circuit design. Finally, the write yield is related to the error rate. Thus, the write yield is easily predicted from a small number of measured samples or the differential coefficients of the CWLM on the Vth's calculated by the SPICE simulation.
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