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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 6, Issue 3, May 2012

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Volume 6, Issue 3

May 2012

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    • Non-recursive decimation filters with arbitrary integer decimation factors
      • Author(s): K. Mondal  and  S. Mitra
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 141 –151
      • DOI:  10.1049/iet-cds.2011.0240
      • Type: Article
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      • p. 141 –151 (11)
        Cascaded integrator comb (CIC) filters are in wide use in oversampled analog-to-digital converters. In this study, the authors advances three new cascaded decimator structures with integer coefficients designed using a polynomial factorisation approach. Each one of the designed decimators shows better stopband attenuation for a given order and decimation factor than the CIC or recently proposed generalised comb filter (GCF) and may not require any prefilter for performance enhancement. A fourth new decimator structure is a hybrid between the CIC and GCF with coefficients approximated by integers. Decimator power dissipation analysis and optimisation have previously been done either by counting the number of additions per sample rate or by focusing on register clock distribution. The authors propose a new metric for estimating the power dissipation of a filter structure from its architecture accounting for dissipation both in the adder cells and the flip-flops. The authors show frequency domain characteristics and compare power dissipations of all the new structures using a representative example.
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      On the use of Karatsuba formula to detect errors in GF((2n)2) multipliers
      • Author(s): S. Pontarelli  and  A. Salsano
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 152 –158
      • DOI:  10.1049/iet-cds.2011.0278
      • Type: Article
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      • p. 152 –158 (7)
        Galois fields are widely used in cryptographic applications. The detection of an error caused by a fault in a cryptographic circuit is important to avoid undesirable behaviours of the system that could be used to reveal secret information. One of the methods used to avoid these behaviours is the concurrent error detection. Multiplication in finite field is one of the most important operations and is widely used in different cryptographic systems. The authors propose in this study an error-detection method for composite finite-field multipliers based on the use of Karatsuba formula. The Karatsuba formula can be used in GF((2n)2) field to decrease the hardware complexity of the finite-field multiplier. The authors propose a novel finite-field multiplier with concurrent error-detection capabilities based on the Karatsuba formula. How the error-detection capabilities of this multiplier are able to face a wide range of fault-based attacks is also shown.
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      Configuration for realising a current-mode universal filter and dual-mode quadrature single resistor controlled oscillator
      • Author(s): K.K. Abdalla ; D.R. Bhaskar ; R. Senani
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 159 –167
      • DOI:  10.1049/iet-cds.2011.0160
      • Type: Article
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      • p. 159 –167 (9)
        A new universal single input multiple output (SIMO)-type universal filter configuration using three dual output current conveyors (DOCCII) and five grounded passive elements is proposed which can realise all the five basic filtering functions namely low pass, high pass, band pass, band stop and all pass in current mode from the same configuration. With appropriate modification of one connection, the circuit can also be converted into a quadrature oscillator capable of providing two voltage mode outputs and as well as two current mode outputs in quadrature. The workability of the new configuration has been demonstrated by simulation program with integrated circuit emphasis (SPICE) simulation results based on a complementary metal oxide semiconductor field effect transistor current conveyor II (CMOS CCII) implemented in 0.35-µm technology.
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      High-Q metamaterial interdigital transmission line based on complementary spiral resonators for low phase noise voltage-controlled oscillator
      • Author(s): J. Choi  and  C. Seo
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 168 –175
      • DOI:  10.1049/iet-cds.2011.0154
      • Type: Article
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      • p. 168 –175 (8)
        In this study, the high-quality factor (Q) metamaterial interdigital transmission line (TL) based on the complementary spiral resonators (CSRs) is presented for reducing the phase noise of the voltage-controlled oscillator (VCO). The high-Q metamaterial TL is realised by adopting the array of the CSRs etched on the ground plane and the interdigital centre line on the signal plane. The interdigital centre line on the signal plane has been used to obtain higher Q value than that of the conventional implementation. The resonance properties and inherent Q value saturation of the proposed high-Q metamaterial interdigital TL have been analysed as follows: width of the centre line on the signal plane, dimensions of the CSRs, current directions between the CSRs, number of the unit cell-pair of the CSRs and whether or not there is the interdigital structure. The phase noise and tuning range of the proposed VCO are −127.50 to −124.87 dBc/Hz at 100 kHz and 5.744–5.86 GHz.
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      Multi-resolution based sensitivity analysis of complex non-linear circuits
      • Author(s): S. Barmada ; A. Musolino ; R. Rizzo ; M. Tucci
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 176 –186
      • DOI:  10.1049/iet-cds.2010.0429
      • Type: Article
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      • p. 176 –186 (11)
        This study addresses the sensitivity analysis of non-linear circuits in their transient and periodic behaviour. The circuits here considered are built of connections of N-ports with frequency-dependent parameters whose input and output quantities are expanded in the wavelet domain. The use of wavelet instead of the Fourier analysis allows a significant increase in the sparsity of the matrices with a comparable accuracy and convergence rate. In addition, by using the proper wavelet basis, it is possible to analyse both the steady state and the transient behaviour. The adjoint system method is used to obtain the sensitivities of the response of the circuit with respect to the design parameters. The multiport connection is described in terms of scattering parameters and the hierarchical approach is extended to the adjoint system. Computational aspects are discussed and examples of application of the proposed technique are reported. The results are compared with those obtained by the use of other techniques.
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      High-quality factor asymmetric-slope band-pass filters: a fractional-order capacitor approach
      • Author(s): P. Ahmadi ; B. Maundy ; A.S. Elwakil ; L. Belostotski
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 187 –197
      • DOI:  10.1049/iet-cds.2011.0239
      • Type: Article
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      • p. 187 –197 (11)
        This study presents new techniques for implementing continuous-time second-order band-pass filters with high-quality factors and asymmetric slopes. The techniques are centred around the realisation of two non-conventional transfer functions which include the non-integer-order Laplacian operator sα; 0<α<1. Four main possible circuit realisations; one based on a frequency-dependent negative resistor (FDNR), another based on an inductor and two based on multiple amplifier biquads (MABs) are given and verified using Spice and experimentally for both transfer functions. In addition, a field programmable analogue array (FPAA) realisation is tested and verified. Last but not least, a possible realisation using current conveyors is also given, tested and verified.
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      Subthreshold CMOS voltage reference circuit with body bias compensation for process variation
      • Author(s): H. Luo ; Y. Han ; R.C.C. Cheung ; G. Liang ; D. Zhu
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 198 –203
      • DOI:  10.1049/iet-cds.2011.0170
      • Type: Article
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      • p. 198 –203 (6)
        This study presents a subthreshold complementary metal oxide semiconductor (CMOS) voltage reference circuit that adopts dynamical body bias to compensate the process-related reference voltage fluctuation. The proposed circuit generates a mean reference voltage of 0.781 V at 1.2 V supply and 27°C, reduces the standard deviation (σ) of the reference voltage from 11 mV to only 3 mV, and meanwhile improves the power supply rejection ratio from −30.7 to −51.4 dB. The average temperature coefficient measured from 0 to 100°C is 48 ppm/°C, and the line regulation is 0.34%/V in a supply voltage ranging from 1.2 to 2.3 V. The maximum supply current is 8.1 µA at 1.2 V supply and 100°C, and the chip area is 0.0533 mm2 in 0.13-µm CMOS technology.
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      Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate
      • Author(s): S.K. Saha
      • Source: IET Circuits, Devices & Systems, Volume 6, Issue 3, p. 204 –210
      • DOI:  10.1049/iet-cds.2011.0252
      • Type: Article
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      • p. 204 –210 (7)
        The study presents the dependence of floating gate (FG) coupling potential, VFG on the source line (SL) programming voltage, VSL of the split-gate flash memory cells with an additional top coupling gate above FG, called the ‘SG-TCG’ cells. The mathematical analysis shows non-linear VFG against VSL behaviour of SG-TCG cells depending on the operation region of FG-MOSFETs. It is found that as the value of VSL increases, the value of VFG initially increases steeply, then gradually and finally, linearly with a lower slope. This anomalous VFG against VSL behaviour is because of the potential drop in the bulk of FG-MOSFETs by the applied VSL. The mathematical analysis, also, shows SL coupling factor (κSL) roll-off because of the increase in the FG-MOSFETs body potential with the increase in VSL. In addition, κSL is shown to approach a constant value in the saturation region of FG-MOSFETs where VFG is less susceptible to supply voltage fluctuation. The mathematical analysis agrees very well with the numerical device simulation. The study, clearly, shows that in order to achieve higher shift in programme cell threshold voltage and reduce performance variability owing to supply voltage fluctuation, the target programming bias VSL of nanoscale SG-TCG cells must be higher than the saturation voltage of FG-MOSFETs.
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