Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 5, Issue 6, November 2011
Volumes & issues:
Volume 5, Issue 6
November 2011
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- Author(s): D.-O. Han ; J.-H. Kim ; K.-D. Lee ; S.-G. Park ; S.-M. Oh ; E.-J. Kim
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 433 –441
- DOI: 10.1049/iet-cds.2010.0334
- Type: Article
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p.
433
–441
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A dual-band fully integrated transceiver for IEEE 802.11a/b/g/j/n wireless local area network (WLAN) was implemented using 0.13 µm complementary metal-oxide semiconductor technology. The proposed hybrid up/down-conversion architecture, which is mixed double- and direct-conversion, was employed in 5 and 2.4 GHz bands, respectively, in order to eliminate the needs for high local-oscillator frequency generations. The hybrid up/down conversion transceiver was archived with small silicon size by block sharing, including such things as mixer sharing for each band, low-pass filter sharing between RX and TX chain and load inductor sharing of the low-noise amplifier and mixer of the Rx chain. The error vector magnitude (EVM) limit of the proposed receiver was measured to be 3.4/3.1% in the 2.4/5 GHz band, respectively. The Tx EVM was measured under the average output power of +12 dBm with external power amplifier to be 2.9/3.5% in the 2.4/5 GHz band, respectively. - Author(s): K. Bhattacharyya and P. Mandal
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 442 –450
- DOI: 10.1049/iet-cds.2010.0439
- Type: Article
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p.
442
–450
(9)
Switch capacitor DC–DC converter is an emerging concept for high dropout application. This paper discusses techniques for output voltage ripple reduction of an embedded dual-switch capacitor – linear regulator-based hybrid DC–DC converter. In spite of deploying the advantage of PSRR property of the linear regulator, the ripple at the output of the convertor is still high. To alleviate this, a new technique of further reduction of the output ripple by introducing synthesised counter ripples through the linear regulator is presented. The conventional and new technique of ripple reduction has been analysed with the help of small signal equivalent circuits. These techniques have been implemented with a hybrid converter for 3.3 V-to-1.35 V conversions. A test chip is fabricated in a 0.18-µm standard digital CMOS process to demonstrate the efficacy of the proposed technique. It is found that the trend of ripple reduction by ripple synthesiser in measured results is consistent with the simulation results and also observed in the measured results that the ripple synthesiser reduces the output ripple of a hybrid converter by the factor of 0.52 and 0.45 for the load current of 2.2 mA and 7.3 mA, respectively. - Author(s): R.-J. Wai ; Y.-W. Lin ; H.-C. Yang
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 451 –461
- DOI: 10.1049/iet-cds.2011.0053
- Type: Article
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p.
451
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This study mainly focuses on the development of a total sliding-mode control (TSMC) strategy for a Chua's chaotic circuit. The TSMC scheme, which is insensitive to uncertainties including parameter variations and external disturbance in the whole control process, comprises the baseline model design and the curbing controller design. In the baseline model design, a computed torque controller is designed to cancel the non-linearity of the nominal plant. In the curbing controller design, an additional controller is designed using a new sliding surface to ensure the sliding motion through the entire state trajectory. Therefore the controlled system has a total sliding motion without a reaching phase in the TSMC system. The effectiveness of the proposed TSMC scheme is verified by experimental results, and the advantages of good transient response and robustness to uncertainties are indicated in comparison with a conventional sliding-mode control system. - Author(s): S. Askari ; M. Nourani ; A. Namazi
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 462 –470
- DOI: 10.1049/iet-cds.2011.0042
- Type: Article
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p.
462
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Analogue and digital circuits are both prone to failure because of device degradations, transient upsets and large parametric variations. Redundancy techniques, such as N-tuple modular redundancy, have been widely used to correct faulty behaviour of components and achieve high reliability for digital circuits. In this study, the authors propose a redundancy based fault-tolerant methodology for analogue circuits. In particular, the authors focus on highly reliable analogue-to-digital converter, which is a critical component in many mixed-signal systems. The authors methodology employs redundant analogue blocks and chooses the best result using an innovative analogue voter. Simulation results are reported to verify the concepts, measure the system's reliability and trade off reliability against cost and power. - Author(s): M.M. Wong ; M.L.D. Wong ; A.K. Nandi ; I. Hijazin
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 471 –476
- DOI: 10.1049/iet-cds.2010.0435
- Type: Article
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In this study, the authors categorise all of the feasible constructions for the composite Galois field GF(((22)2)2) Advanced Encryption Standard (AES) S-box into four main architectures by their field representations and their algebraic properties. For each of the categories, a new optimisation scheme which exploits algebraic normal form representation followed by a sub-structure sharing optimisation is presented. This is performed by converting the subfield GF((22)2) inversion into several logical expressions, which will be in turn reduced using a common sub-expression elimination algorithm. The authors show that this technique can effectively reduce the total area gate count as well as the critical path gate count in composite field AES S-boxes. The resulting architecture that achieves maximum reduction in both total area coverage and critical path gate count is found and reported. The hardware implementations of the authors proposed AES S-boxes, along with their performance and cost are presented and discussed. - Author(s): D. Schinke ; S. Priyadarshi ; W. Shepherd Pitts ; N. Di Spigna ; P. Franzon
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 477 –483
- DOI: 10.1049/iet-cds.2010.0410
- Type: Article
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The majority of nanocrystal floating gate research has been done at the device level. Circuit-level research is still in its early stages because of the lack of a physical device model appropriate for circuit simulations. In this study, a comprehensive and accurate SPICE-compatible physical equation-based model of nanocrystal floating gate devices is developed based on uniform direct tunnelling and Fowler–Nordheim tunnelling. The main contribution is a Verilog-A module that captures the physical behaviours of programming and erasing the device. A predictive NMOS model is then used for modelling the conduction channel to determine the behavioural I–V characteristics. The proposed model uses only explicit formulae resulting in fast computation appropriate for circuit simulation and can be used in any SPICE simulator supporting Verilog-A. It interacts dynamically with the rest of the circuit and includes charge leakage which enables power consumption analysis. The simulation results of the proposed model fit well to experimental results of various fabricated devices. Additionally, it is verified in HSPICE, demonstrating a significant speedup and good agreement with a numerical device simulator. This study is important in bridging the gap between device- and circuit-level research. - Author(s): L. Xia ; H. Chen ; Y. Huang ; Z. Hong ; P.Y. Chiang
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 484 –493
- DOI: 10.1049/iet-cds.2011.0112
- Type: Article
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Receiver timing synchronisation is a significant challenge for impulse radio ultra-wideband (IR-UWB) systems due to the low received power and narrow pulse width. In a coherent receiver, the local template pulses need to be synchronised with the received pulses with a precision of tens of picoseconds. Because of the periodic reduction in received correlated power, the traditional two-stage synchronisation method (acquisition and tracking) is not suitable for a single-path IR-UWB receiver. A tracking only, dual-loop delay-locked loop (DLL) with a 100 ps minimum phase shift is proposed to overcome this issue. This dual-loop DLL, employing a higher frequency fine loop, exhibits a better jitter transfer characteristic compared with a conventional dual-loop DLL. Measurement results of a 130 nm CMOS prototype indicate a locking frequency range of 30–120 MHz, and a best output jitter of 5.9 ps-rms (input reference jitter is 2.9 ps-rms). The total power consumption is 1.8 mW with a 1.2 V supply voltage. - Author(s): P. Sumathi and P.A. Janakiraman
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 494 –504
- DOI: 10.1049/iet-cds.2010.0323
- Type: Article
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The frequency tracking performance of sliding discrete Fourier transform (SDFT)-based phase locking (PLL) scheme has been improved by supplementing a cosine look-up table (cLUT) loop. Since the SDFT algorithm is marginally stable, to avoid instability, a damping factor is introduced, which causes the steady-state error in the PLL behaviour. The addition of cLUT indirectly strengthens cosine component of SDFT output and eliminates the effect of damping factor. Consequently, the numerically controlled oscillator (NCO) yields accurate sampling frequency, and it could be utilised to generate unit sine and cosine reference signals, synchronous with the periodic input signal in power system applications. A mathematical model of the look-up table (LUT) assisted SDFT-based PLL has been developed to analyse the transient and steady-state behaviour and it substantiates the improvement in steady-state performance. The PLL exhibits second order under damped response resulting in faster acquisition and small reduction in pull-in range with zero steady-state error. The improvement in performance of the LUT-assisted SDFT PLL is investigated by simulation and experimental studies. - Author(s): E. Nigussie ; S. Tuuna ; J. Plosila ; P. Liljeberg ; J. Isoaho ; H. Tenhunen
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 505 –517
- DOI: 10.1049/iet-cds.2010.0300
- Type: Article
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The authors present a performance boosting technique with a better power efficiency for delay-insensitive on-chip interconnects. The increase in signal propagation delay uncertainty with technology scaling makes self-timed delay-insensitive on-chip interconnects the most appropriate alternative. However, achieving high-performance communication in self-timed delay-insensitive links is difficult, especially for large bit parallel transmission because of the time-consuming detection of each bit validity. The authors present a high-speed completion detection technique along with its circuit implementation and two on-chip interconnects which use the proposed completion detection circuit. The performance, power consumption, power efficiency and area of the presented on-chip interconnects are analysed and compared with the conventionally implemented delay-insensitive interconnects. For 64-bit parallel transmission, 2.07 and 1.72 times throughput improvement with 47 and 39% more power efficiency have been achieved for the two interconnects compared to their conventional counterparts. The interconnect circuits are designed and simulated using Cadence Analog Spectre and Hspice with 65 nm complementary metal–oxide semiconductor technology from STMicroelectronics. - Author(s): T. Choogorn and J. Mahattanakul
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 518 –526
- DOI: 10.1049/iet-cds.2011.0050
- Type: Article
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A relationship between common-mode rejection and differential-mode distortion of the fully differential ladder Gm-C filters employing pseudo-differential transconductors is investigated. The equation which relates differential-mode HD3 and common-mode gain of the Nth-order ladder Gm-C filters is derived. It has been found that in the cases where the inverter-based pseudo-differential transconductors are employed, the HD3 level of the odd-order filter is always lower than that of the even-order filter. By using the derived equation with the extracted parameters of certain inverter-based transconductors, it was found that by varying the common-mode gain from 0 to 1, the HD3 of the odd-order filters and even-order filters are decreased by 4.9 dB and increased by 3.1 dB, respectively. Simulation results are found to be in good agreement with the derived equation. - Author(s): D.V. Kamat ; P.V. Ananda Mohan ; K. Gopalakrishna Prabhu
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 6, p. 527 –535
- DOI: 10.1049/iet-cds.2011.0092
- Type: Article
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In this study, the design of active-RC filters using opamps with and without feed-forward-compensation is considered. Accurate analysis of the passive compensation scheme suggested in literature for lossless and lossy integrators using feed-forward-compensated opamps is carried out. The compensation for the lossy and lossless integrators using negative impedance converter for active filters using two cascaded gms in place of opamps is explored. Novel building blocks for realising the negative capacitance needed for exact compensation are proposed. To study the efficacy of the proposed compensation technique, a two-integrator loop biquad is considered. The PSPICE simulation results of Tow-Thomas biquad are presented to highlight the performance improvement obtained using the proposed compensation techniques.
Fully integrated dual-band transceiver for IEEE 802.11a/b/g/j/n wireless local area network applications with hybrid up/down conversion architecture
Technique for the reduction of output voltage ripple of switched capacitor-based DC–DC converters
Experimental verification of total sliding-mode control for Chua's chaotic circuit
Fault-tolerant A/D converter using analogue voting
Composite field GF(((22)2)2) Advanced Encryption Standard (AES) S-box with algebraic normal form representation in the subfield inversion
SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation
100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation
Phase locking scheme based on look-up-table-assisted sliding discrete Fourier transform for low-frequency power and acoustic signals
Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects
Relationship between common-mode rejection and differential-mode distortion in fully differential Gm-C filters
Active-RC filters using two-stage OTAs with and without feed-forward compensation
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