Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 5, Issue 5, September 2011
Volumes & issues:
Volume 5, Issue 5
September 2011
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- Author(s): P. Malík
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 351 –359
- DOI: 10.1049/iet-cds.2010.0223
- Type: Article
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p.
351
–359
(9)
Modified discrete cosine transform (MDCT) is used in many audio coding standards for time-to-frequency transformation of digital signals. It is one of the most computationally intensive operations in audio compression and decompression processes. In this study, optimised dedicated hardware architectures utilised in a highly scalable MDCT IP core are proposed to accelerate the forward/backward MDCT computation in MP3 audio coding standard. The MDCT IP core is pipelined, capable to compute both the forward and backward MDCT on the same hardware and it is optimised with field-programmable gate arrays (FPGA) and application-specific integrated circuit (ASIC) technologies. The MDCT IP core is implemented to FPGA and ASIC, whereby the FPGA implementation used Xilinx Virtex-4 FPGA, while the ASIC implementation used AMS 350 nm CMOS standard cell library. The MDCT IP core is further optimised and implemented utilising UMC 90 nm CMOS low-power digital libraries and clock gating technique. As a result, power consumption and the area are reduced significantly. The proposed hardware architectures are optimised to achieve high computational speed with high precision, and therefore they are suitable for a lossless audio compression. In particular, high computational speed permits multichannel real-time acceleration of the forward and backward MDCT computation. - Author(s): E.A. Sobhy ; S. Pentakota ; Z. Yu ; S. Hoyos
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 360 –364
- DOI: 10.1049/iet-cds.2010.0383
- Type: Article
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p.
360
–364
(5)
Stringent jitter specifications in the sampling clocks severely limit the evolution of future generations of wideband high-performance receivers. For instance, it is shown that a conventional single-channel receiver requires 1.5 ps of jitter standard deviation to achieve 34 dB signal-to-noise ratio (SNR) when sampling a 10 GHz orthogonal frequency division multiplexing (OFDM) signal. This study presents an analytical framework for the design of jitter-tolerant multi-channel filter-bank OFDM receivers. Additionally, the study presents an optimisation method for the filter-bank bandwidth that is able to reduce the filter-bank order saving power and area and achieving optimal signal quality. Simulations that confirm the analytical result show that 34 and 38 dB SNR are achieved with 5-channel and 10-channel receivers, respectively, when using second-order bandwidth-optimised filter-bank that samples a 10 GHz OFDM signal tolerating 6 ps of jitter. - Author(s): K.C. Narasimhamurthy and R. Paily
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 365 –370
- DOI: 10.1049/iet-cds.2010.0424
- Type: Article
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p.
365
–370
(6)
The authors present the wafer scale fabrication and characteristics of back-gate semiconducting carbon nanotube thin-film field-effect transistors (SN-TFTs) suitable for high-current applications. Good on–off current ratio TFTs using affordable 95% purity semiconducting tubes by appropriately choosing the length of the nanotubes and improving the nanotube density have been demonstrated. Moreover, the nanotube thin-film deposition is carried out using a simple solution-based assembly method and good TFT performance and high currents are achieved with random-oriented network of nanotubes. Hafnium oxide (HfOx) is used as the gate dielectric material to improve the device performance. The global gate devices have shown an excellent p-type behaviour with a low output conductance value of 0.3 µS. The SN-TFTs have exhibited a maximum on–off ratio of 4×104 at lower operating gate voltages, a maximum on-current of 3.1 mA at a current density of 6.2 µA/µm, a steep sub-threshold slope of 600 mV/decade, threshold voltage of −1.5 V, a maximum normalised transconductance of 0.7 µS/µm and a maximum carrier mobility of 44.2 cm2/V s. - Author(s): J.J. Cooley ; A.-T. Avestruz ; S.B. Leeb
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 371 –383
- DOI: 10.1049/iet-cds.2010.0401
- Type: Article
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p.
371
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(13)
An analytical modelling approach for fully differential amplifiers is presented and validated through examples. Separation of the analysis into two steps coupled with linear superposition techniques leads to concise mathematical expressions. An added benefit of the two-step approach is that the usual symmetry assumptions are not needed. As a consequence, the results hold for arbitrary element values. The mathematical results are validated by comparison to SPICE simulations and experimental data. - Author(s): C.H. Tsai and J.H. Wang
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 384 –391
- DOI: 10.1049/iet-cds.2010.0309
- Type: Article
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p.
384
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(8)
A capacitor-less low-power low-dropout regulator (LDR) with a slew-rate-enhanced circuit (SRE) was proposed. The SRE uses six transistors to constitute two comparators and two auxiliary transistors. The comparators sense the variation of load current to control one of the auxiliary transistors that generate a large current to charge or discharge the gate capacitor of the power transistor; thus SRE increases the slew-rate at the gate of the power transistor. The quiescent current of the LDR remains 18 µA at the steady state because the auxiliary transistors work at the cut-off region to reduce power consumption. When load current changes between 0.1 and 100 mA, the variation of the output voltage of the LDR is improved from 675 to 300 mV. - Author(s): X.G. Sun ; B.Y. Chi ; C. Zhang ; Z.Q. Wang ; Z.H. Wang
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 392 –402
- DOI: 10.1049/iet-cds.2010.0291
- Type: Article
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p.
392
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(11)
Ultra-high-frequency radio frequency identification reader receiver is implemented in 0.18 µm CMOS. Based on the key parameter analysis for the reader receiver, the dynamic range concept is proposed to define the specifications and evaluate the performance of a reader receiver. The presented receiver utilises a quadrature direct-conversion architecture which consists of passive mixers, baseband programmable gain amplifiers (PGAs) and low-pass filters (LPFs). Both good input matching and as high as 10 dBm input P1 dB of the RF front-end is achieved by utilising the passive mixers driven by square wave local oscillators. In the analogue baseband, four PGAs provide a gain control range higher than 80 dB and the LPFs have a reconfigurable bandwidth from 100 kHz to 1.6 MHz to optimise noise performance under different Rx data rates. The on-chip DC-blocker with controllable cut-off frequency is proposed to avoid DC offset problems and obtain a fast settling time simultaneously. In the normal mode, the receiver sensitivity achieves −74 dBm with 12.9 dB output signal-to-noise ratio. An alternative radio frequency receiving path with a low noise amplifier (LNA) improves the receiver sensitivity in the listen-before-talk mode by 14 dB. The total power dissipation is only 58 mW with 1.8 V supply voltage. - Author(s): S. Shedabale ; G. Russell ; A. Yakovlev
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 403 –410
- DOI: 10.1049/iet-cds.2010.0110
- Type: Article
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p.
403
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(8)
The effects of process variations on the performance of nanometre CMOS circuits have become a serious design issue, aggravated by further scaling of device dimensions. This article presents a statistical TCAD tool called Multilevel-Partitioned REsponse Surface Modelling (M-PRES) to model the impact of manufacturing process variations on circuit performance; an SRAM cell is used as a demonstration vehicle for the tool. A new non-Gaussian approach for modelling variations for sub-90 nm technologies is also presented. A comparison is made with the Monte Carlo approach, demonstrating four times (4×) computationally efficiency for M-PRES without the loss of accuracy. The M-PRES models are also re-usable reducing the computation time for the analysis of other sets of process data down to a few tens of seconds. - Author(s): H.-Y. Lee
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 411 –417
- DOI: 10.1049/iet-cds.2010.0329
- Type: Article
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p.
411
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(7)
A zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter (ADC) using an offset compensation method is presented. The ADC has been fabricated by 0.18 µm CMOS process with a die area of 0.69 mm2. While the common-mode voltage tracking circuit is turned on, for an input signal of 41 MHz with the sampling rate of 100 MS/s, the measured SNDR is 43.82 dB with effective number of bits 7.0-bit, the DNL ±0.79-LSB and the INL ±1.24-LSB. The power is 8 mW at a supply voltage of 1.8 V. - Author(s): G. Blakiewicz
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 418 –423
- DOI: 10.1049/iet-cds.2010.0431
- Type: Article
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p.
418
–423
(6)
An improved flipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator are presented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the output current change from low to high value and poor stability for large capacitive load. The most important parameters of the modified FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improved one are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS 0.35 µm technology. The measurement results of a test circuit show its relatively high current efficiency of 74 and 99.93% for output current 100 µA and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mV for output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 µs, and load capacitance 0–100 pF. - Author(s): Y.-T. Hwang and W.-D. Chen
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 5, p. 424 –432
- DOI: 10.1049/iet-cds.2010.0143
- Type: Article
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p.
424
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(9)
Complex QR factorisation is a fundamental operation used in various applications such as adaptive beamforming and MIMO signal detection. In this paper, based on Givens rotation scheme, a high-throughput, fully parallel complex-valued QR factorisation (CQRF) design is presented. It features the lowest computing complexity in various factorising schemes and indicates no BER performance loss when applied to a MIMO signal detection system. Via carefully plotted scheduling, one CQRF computation can be completed in eight clock cycles. In hardware design, a low complexity and look-up-table-free CORDIC algorithm is employed to implement the rotation operations. Further design optimisations, such as hardware sharing of common modules and reduction of register usage by shortening the variable's life span, are also applied. Sized 2×2 and 4×4 chip designs largely following the IEEE 802.11n standard are developed. The implementation results in TSMC 0.18 um process technology show that the proposed 4×4 design, with a gate count of only 134.6 K, is capable of performing 15 M CQRFs per second. The measured power consumption is 196.3 mW at 120 MHz. Compound performance indexes such as area-time product and energy consumption per CQRF also indicate significant performance edges of the proposed designs.
Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC
Analytical framework and bandwidth optimisation of orthogonal frequency division multiplexing low-order multi-channel filter-bank receivers for achieving sampling clock-jitter robustness
Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes
Small-signal analysis of fully-differential closed-loop op-amp circuits with arbitrary external impedance elements
Capacitor-less low-dropout regulator with slew-rate-enhanced circuit
Ultra-high-frequency radio frequency identification reader receiver with 10 dBm input P1 dB and −74 dBm sensitivity in 0.18 µm CMOS
M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parameters
Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation
Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower
Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips
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