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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 5, Issue 5, September 2011

Volume 5, Issue 5

September 2011

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    • Highly scalable IP core to accelerate the forward/backward modified discrete cosine transform in MP3 implemented to FPGA and low-power ASIC
      Analytical framework and bandwidth optimisation of orthogonal frequency division multiplexing low-order multi-channel filter-bank receivers for achieving sampling clock-jitter robustness
      Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes
      Small-signal analysis of fully-differential closed-loop op-amp circuits with arbitrary external impedance elements
      Capacitor-less low-dropout regulator with slew-rate-enhanced circuit
      Ultra-high-frequency radio frequency identification reader receiver with 10 dBm input P1 dB and −74 dBm sensitivity in 0.18 µm CMOS
      M-PRES: a statistical tool for modelling the impact of manufacturing process variations on circuit-level performance parameters
      Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation
      Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower
      Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips

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