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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 3, Issue 4, August 2009

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Volume 3, Issue 4

August 2009

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    • Driver circuits for temperature-invariant performance of junction diodes
      • Author(s): S.C. Bera ; R.V. Singh ; V.K. Garg
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 143 –152
      • DOI:  10.1049/iet-cds.2008.0266
      • Type: Article
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      • p. 143 –152 (10)
        Different types of driver circuits for the temperature-invariant brightness of light emitting diodes and the RF performance of Schottky barrier diodes, p–i–n diodes and p–n junction diodes are presented. The sensitivities of the proposed driver circuits with ambient temperature, bias voltage and other component variations are presented. Novel techniques are proposed and demonstrated to compensate the performance variation of diode-based circuits due to the temperature sensitivity of the components of driver circuits. The proposed driver circuits eliminate the requirement of conventional temperature compensation techniques with temperature sensors. The driver circuits respond directly to the junction temperature of the diodes itself; thus, there will be no compensation error due to the temperature gradient or self-heating of the diodes. This technique is very simple, accurate and easy to implement.
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      Quadrature oscillator using grounded components with current and voltage outputs
      • Author(s): S. Maheshwari
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 153 –160
      • DOI:  10.1049/iet-cds.2009.0072
      • Type: Article
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      • p. 153 –160 (8)
        This study proposes new third-order quadrature oscillator that provides several voltage and current outputs simultaneously. The circuit uses differential voltage current conveyors and grounded components, enjoys non-interactive frequency control and can be made resistor-less by using voltage-controlled differential voltage current conveyors. Non-ideal study and parasitic effects are also considered and their effects are discussed. The proposed theory is verified through PSPICE by good results.
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      Feedforward simple control technique for on-chip all-digital three-phase AC/DC power-MOSFET converter with least components
      • Author(s): J.-J. Chen ; C.-M. Kung ; Y.-S. Hwang
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 161 –171
      • DOI:  10.1049/iet-cds.2008.0361
      • Type: Article
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      • p. 161 –171 (11)
        A novel simple control technique for on-chip all-digital three-phase alternating current to direct current (AC/DC) power-metal oxide semiconductor field-effect transistors (MOSFET) converter with least components, which is employed to obtain small current and DC output voltage ripples as well as excellent performance, and using a feedforward simple control method for DC output voltage regulation is proposed. The proposed all-digital feedforward controller has the features of low cost, simple control, fast response, independence of load parameters and the switching frequency, it has no need for compensation, and high stability characteristics; moreover, the proposed controller consists of three operation amplifiers and few digital logic gates that are directly applied to the three-phase converter. The power-MOSFETs are also known as power switches, whose control signals are derived from the proposed all-digital feedforward controller. Instead of thyristors or diodes, the application of power-MOSFETs can reduce the loss of AC/DC converter that is proper to the power supply system. The input stage of an AC/DC converter functions as a rectifier and the output stage is a low pass inductor capacitor (LC) filter. The input AC sources may originate from miniature three-phase AC generator or low-power three-phase DC/AC inverter. The maximum output loading current is 0.8 A and the maximum DC output ripple is less than 200 mV. The prototype of the proposed AC/DC converter has been fabricated with Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm 2P4M complementary MOS (CMOS) processes. The total chip area is 2.333×1.960 mm2. The proposed AC/DC converter is suitable for the following three power systems with the low power, DC/DC converter, low-dropout linear regulator and switch capacitor. Finally, the theoretical analysis is verified to be correct by simulations and experiments.
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      Scalable and bijective cells for C-testable iterative logic array architectures
      • Author(s): B.-Y. Ye ; P.-Y. Yeh ; S.-Y. Kuo ; I.-Y. Chen
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 172 –181
      • DOI:  10.1049/iet-cds.2008.0296
      • Type: Article
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      • p. 172 –181 (10)
        In this study, a novel idea is proposed to test arithmetic circuits with both acceptable number of test patterns (NTP) and hardware overhead (HO). First, highly scalable full adder and full substractor are proposed. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between the NTP and the HO, which is a function of n. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. An iterative logic array (ILA) based on these scalable cells will still be C-testable. Based on the novel bijective and scalable cells, the authors propose C-testable designs for multiplier-accumulator (MAC), N-tap finite impulse response (FIR) filter and matrix multiplication, where the (HO, NTP) pairs with n=2 are only about (4.87%, 74). For 4×4 matrix multiplication, the total test time of the proposed method is only about 0.19% of that with the scan-chain method. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA and save lots of test pins and build-in self-test (BIST) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results. The proposed technique makes the ILA-based DFT schemes more practical, systematic and useful for real-world complex applications.
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      Bootstrapped inverter using a pentacene thin-film transistor with a poly(methyl methacrylate) gate dielectric
      • Author(s): Y. Yun ; C. Pearson ; M.C. Petty
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 182 –186
      • DOI:  10.1049/iet-cds.2009.0066
      • Type: Article
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      • p. 182 –186 (5)
        A bootstrapped inverter incorporating pentacene organic thin-film transistors (OTFTs), with poly(methyl methacrylate) as the gate dielectric, has been designed, fabricated and tested. The inverter uses capacitive coupling and bootstrapping effects, and exhibits superior performance to the normal diode-connected load inverter. The pentacene OTFTs used for the inverter possess a field-effect mobility of 0.32 cm2/V/s, a threshold voltage of −10.0 V, a subthreshold slope of 1.5 V per decade and an on/off current ratio of 2.2×106. The inverter has a 30 µs rise time and a 450 µs fall time, at an operating frequency of 1 kHz and 30 V drive voltage.
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      Ladder-simulation elliptic bandpass active-RC filter structure employing identical resistors
      • Author(s): J. Mahattanakul ; P. Khumsat ; W. Surakampontorn
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 187 –196
      • DOI:  10.1049/iet-cds.2009.0026
      • Type: Article
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      • p. 187 –196 (10)
        A novel structure of the ladder-based elliptic bandpass active-RC filter is presented. Unlike the previously reported elliptic bandpass active-RC filter, the proposed filter contains resistors with identical value and is therefore more suitable for integrated-circuit realisation. Also, according to the simulation results, the proposed elliptic bandpass filter performs better than the reciprocator-based active-RC filter, which employs identical resistors, in terms of noise, power and area. Additionally, the proposed filter structure was also found to be less sensitive than both of the aforementioned structures.
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      Development of a re-configurable ambisonic decoder for irregular loudspeaker configuration
      • Author(s): P.W.M. Tsang  and  K.W.K. Cheung
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 4, p. 197 –203
      • DOI:  10.1049/iet-cds.2009.0007
      • Type: Article
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      • p. 197 –203 (7)
        This study reports a heuristic genetic algorithm to determine the decoding parameters in a first-order ambisonic system for reconstructing a three-dimensional sound field with an arbitrary quad speaker configuration. On this basis, a hardware prototype has been developed using a field programmable gate array (FPGA) to decode ambisonic signals that are encoded in the standard B-format. To allow direct coupling with digital audio sources, the input and output channels of the decoder are implemented with the I2S interface. Evaluations reveal that the decoding parameters derived by this method are superior to existing approaches in terms of flexibility in loudspeaker configuration and optimisation of some of the essential factors in surround sound reconstruction.
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      Approach to analyse and design nearly sinusoidal oscillators

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