Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887
banner image
image of Volume 2, Issue 5
Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 2, Issue 5, October 2008

Volumes & issues:

Volume 2, Issue 5

October 2008

Show / Hide details

    • Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance
      • Author(s): P. Sakian ; M. Saffari ; M. Atarodi ; A. Tajalli
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 5, p. 409 –421
      • DOI:  10.1049/iet-cds:20080111
      • Type: Article
      • + Show details - Hide details
      • p. 409 –421 (13)
        A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 µm CMOS technology and operating in 10 Gbps data rate, the entire circuit consumes 52 mW.
        Add to favourites
        Export citations
      Improving sensitivity of direct-form switched-capacitor filters by coinciding pole–zero pairs
      • Author(s): F.C. Pontes ; A. Petraglia ; F.A.P. Barúqui
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 5, p. 422 –428
      • DOI:  10.1049/iet-cds:20070297
      • Type: Article
      • + Show details - Hide details
      • p. 422 –428 (7)
        The aim here is to study the inclusion of mutually cancelling pole–zero pairs in the transfer functions of switched-capacitor filters to reduce their sensitivity to capacitance ratios. Combined with an optimum allocation strategy of poles and zeros for the original transfer function, the proposed technique proved effective in comparison with designs developed from classical approximations, such as Butterworth, Chebyshev and elliptic. Spice simulations carried out with a fully differential prototype filter designed in a 0.35 µm CMOS technology are shown to validate the theory. As a result of the extra circuitry to implement a coincident pole–zero pair, the capacitance spread decreased 6-fold and the frequency response deviation decreased by a factor of 2.6 in the passband, whereas the power consumption increased only 13.6%, from 30.2 to 34.3 mW.
        Add to favourites
        Export citations
      VLSI design for MPEG-4 shape coding using a contour-based binary motion estimation algorithm
      • Author(s): T.-H. Tsai  and  C.-P. Chen
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 5, p. 429 –438
      • DOI:  10.1049/iet-cds:20080048
      • Type: Article
      • + Show details - Hide details
      • p. 429 –438 (10)
        An efficient architecture with the fast algorithm for MPEG-4 shape coding is proposed. The authors apply the fast shape coding algorithm, with contour-based binary motion estimation (CBBME), which is based on the properties of a boundary mask. By using the block-matching motion estimation and the extended approach on centre-biased motion vector distribution with shrinking of the search range, a large number of search points in BME can be skipped. Based on this algorithm, a dedicated architecture design using the proposed CBBME algorithm is developed. With certain optimisation and design considerations, the memory access and processing cycles can be reduced. The average number of clock cycles for the processing of one binary alpha block is only 1708, which is only 56% of the previous design. In addition, a prototyping chip for shape coding is implemented and verified. The die area is 2.4×2.4 mm2 with TSMC 0.18 µm CMOS technology and the maximum clock frequency is 53 MHz.
        Add to favourites
        Export citations
      Radio-frequency front-end for 5 GHz wireless local area network transceivers
      • Author(s): A. Italia ; F. Carrara ; A. Scuderi ; E. Ragonese ; C.D. Presti ; G. Sapone ; G. Palmisano
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 5, p. 439 –450
      • DOI:  10.1049/iet-cds:20080018
      • Type: Article
      • + Show details - Hide details
      • p. 439 –450 (12)
        A transceiver front-end for 5 GHz wireless local area network applications has been designed and implemented in a low-cost 46 GHz fT pure-silicon bipolar technology. The transceiver front-end adopts a superheterodyne sliding-IF architecture and consists of a down-converter, an up-converter and an LO frequency synthesiser. By exploiting a 1 bit variable-gain low-noise amplifier, the down-converter is able to provide an excellent noise figure of 4 dB while ensuring an input 1 dB compression point of −10 dBm with a current consumption of 25 mA from a 3 V supply voltage. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1 dB compression point of 5.3 dBm although consuming only 45 mA from a 3 V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35 dB dynamic range. The LO frequency synthesiser is implemented by means of an integer-N phase-locked loop. It features a phase noise of −117 dBc/Hz at 1 MHz offset from the centre frequency of 4.1 GHz and exhibits a tuning range of 1.2 GHz, from 3.47 to 4.65 GHz. The LO frequency synthesiser draws 20 mA from a 3 V supply voltage.
        Add to favourites
        Export citations
      Statistical modelling of the variation in advanced process technologies using a multi-level partitioned response surface approach
      • Author(s): S. Shedabale ; H. Ramakrishnan ; G. Russell ; A. Yakovlev ; S. Chattopadhyay
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 5, p. 451 –464
      • DOI:  10.1049/iet-cds:20080031
      • Type: Article
      • + Show details - Hide details
      • p. 451 –464 (14)
        The advances in semiconductor processing technologies have led to the need for a detailed understanding and stringent control of the variations in device performance. Statistical techniques provide methods, such as response surface modelling (RSM), to measure, characterise and model the variations, thus enabling an understanding and identification of the impact of these on both yield and performance of the devices and circuits built from advanced process technologies. The construction of response surface (RS) models, however, has been restricted to only a few variables, due to the number of TCAD simulations and hence the statistical analyses required for fitting sufficiently accurate models. The problem of modelling a large number of manufacturing process parameters is addressed by partitioning the parameters and subsequently building multi-level RS models which can analyse and predict the process variability. This approach greatly reduces (by approximately two to three orders of magnitude) the large number of TCAD simulations necessary to fit the RS models. The application of multi-level partitioned RSM is demonstrated on a 65 nm CMOS technology. With the device dimensions shrinking and the impact of manufacturing process variations becoming dominant on the device performance, the proposed approach plays a vital role in design for manufacturability. The variability information obtained from these models is important not only to control and optimise the process variation but also to quantify its effects on device and circuits designs.
        Add to favourites
        Export citations
      Comment: Practical voltage/current-controlled grounded resistor with dynamic range extension
      • Author(s): R. Senani  and  D.R. Bhaskar
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 5, p. 465 –466
      • DOI:  10.1049/iet-cds:20080211
      • Type: Article
      • + Show details - Hide details
      • p. 465 –466 (2)
        Recently, Maundy, Gift and Aronhime presented a voltage/current-controlled grounded resistor which makes use of bisection of the drain-to-source voltage of a FET to produce a linear resistor with wide dynamic range extension. The purpose of this communication is to bring on record, in the context of the above paper, our works on the same topic published more than a decade back which are closely related to the work reported in the above-mentioned paper but have not been cited therein.
        Add to favourites
        Export citations
      Reply: Practical voltage/current-controlled grounded resistor with dynamic range extension

Most viewed content for this Journal

Article
content/journals/iet-cds
Journal
5
Loading

Most cited content for this Journal

Print this page
This is a required field
Please enter a valid email address