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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 2, Issue 3, June 2008

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Volume 2, Issue 3

June 2008

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    • Concurrent error detection in GF(2m) multiplication and its application in elliptic curve cryptography
      • Author(s): W. Chelton  and  M. Benaissa
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 289 –297
      • DOI:  10.1049/iet-cds:20070184
      • Type: Article
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      • p. 289 –297 (9)
        A novel approach to achieve concurrent error detection in finite-field multiplication over GF(2m) that uses multiple-bit interlaced parity codes is presented. These codes are implemented as a generic parity checker, which means they can be used with any multiplier architecture. Relative to the number of parity bits used, much improved delay and error‐detection performance are achieved compared to previously reported results, yet for the examples considered the area overhead did not exceed 12%. The proposed work is particularly important for cryptography implementations employing GF(2m) multipliers and requiring reliability and protection against adversarial attacks that use fault induction.
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      Enhancing power analysis attacks against cryptographic devices
      • Author(s): M. Bucci ; L. Giancane ; R. Luzzi ; M. Marino ; G. Scotti ; A. Trifiletti
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 298 –305
      • DOI:  10.1049/iet-cds:20070166
      • Type: Article
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      • p. 298 –305 (8)
        A current-measuring technique is introduced, which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower insertion error are the main advantages with respect to a resistor-based measurement. Experimental results when the proposed circuit is used to measure the current consumption of an FPGA are reported, and the achievable advantage in terms of sensitivity is discussed. Results of a differential power analysis attack are reported too.
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      Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array
      • Author(s): W.-J. Huang  and  S.-I. Liu
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 306 –316
      • DOI:  10.1049/iet-cds:20070343
      • Type: Article
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      • p. 306 –316 (11)
        A capacitor-free CMOS low dropout regulator (LDR) using the nested Miller compensation with an active resistor (NMCAR) is presented. It can efficiently control the damping factor and reduce the required Miller compensation capacitance. It can also resolve the trade-off between dc loop gain and damping factor, which existed in the LDR using the nested Miller compensation. To reduce the total Miller compensation capacitances further, a capacitor-free CMOS LDR using both the NMCAR and a 1-bit programmable capacitor array is presented. For this LDR, the total on-chip compensation capacitance is reduced 40% without influencing its stability. Furthermore, it also enhances the recovery time, compared with the LDR using the NMCAR technique. Two proposed LDRs with bandgap voltage references have been fabricated in a 0.35 µm CMOS process. They can operate with and without output capacitors.
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      Compact CMOS current conveyor for integrated NEMS resonators
      • Author(s): J. Arcamone ; B. Misischi ; F. Serra-Graells ; M.A.F. van den Boogaart ; J. Brugger ; F. Torres ; G. Abadal ; N. Barniol ; F. Pérez-Murano
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 317 –323
      • DOI:  10.1049/iet-cds:20070320
      • Type: Article
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      • p. 317 –323 (7)
        A fully integrated nanoelectromechanical system (NEMS) resonator together with a compact built-in complementary metal–oxide–semiconductor (CMOS) interfacing circuitry is presented. The proposed low-power second generation current conveyor circuit allows measuring the mechanical frequency response of the nanocantilever structure in the megahertz range. Detailed experimental results at different DC biasing conditions and pressure levels are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing based on nanostencil lithography. The proposed readout circuit can be adapted to operate the nanocantilever in closed loop as a stand-alone oscillator.
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      Noise optimised charge-sensitive CMOS amplifier for capacitive radiation detectors
      • Author(s): T. Noulis ; S. Siskos ; G. Sarrabayrouse
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 324 –334
      • DOI:  10.1049/iet-cds:20070223
      • Type: Article
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      • p. 324 –334 (11)
        A low-voltage, low-noise, charge-sensitive preamplifier (CSA) for particle tracking using a silicon strip detector was designed. The preamplifier was optimised in terms of the total output noise performance using a noise minimisation technique based on the MOSFET noise small signal equivalent circuit and readout front-end noise optimisation criteria valid in the strong inversion region. The preamplifier was designed and fabricated in a 0.35 µm CMOS process by Austria Mikro Systeme for a specific silicon strip detector of 2 pF capacitance for X-ray spectroscopy. The circuit exhibits satisfactory performance compatible to the specific low-energy radiation detection application. Particularly, the CSA provides an equivalent noise charge of 254 e−+13.5 e−/pF, consumes 165 µW and achieves an output conversion gain equal to 2.81 mV/fC and a linearity <0.57%. Analysis is supported by extensive measurement results confirming the circuit characteristics and their flexibility to be used in a variety of readout applications.
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      Idealised operation of zero-voltage-switching series-L/parallel-tuned Class-E power amplifier
      • Author(s): M. Thian  and  V. Fusco
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 337 –346
      • DOI:  10.1049/iet-cds:20070153
      • Type: Article
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      • p. 337 –346 (10)
        An analysis of a modified series-L/parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-current derivative switching (ZCDS) conditions should be applied to obtain optimum Class-E operation. On the other hand, when the output transistor capacitance is incorporated in the circuit, i.e. in the modified series-L/parallel-tuned topology, the ZCS and ZCDS would not give optimum operation and therefore zero-voltage-switching (ZVS) and zero-voltage-derivative switching (ZVDS) conditions should be applied instead. In the modified series-L/parallel-tuned Class-E configuration, the output-device inductance and the output-device output capacitance, both of which can significantly affect the amplifier's performance at microwave frequencies, furnish part, if not all, of the series inductance L and the shunt capacitance COUT, respectively. Further, when compared with the classic shunt-C/series-tuned topology, the proposed Class-E configuration offers some advantages in terms of 44% higher maximum operating frequency (fMAX) and 4% higher power‐output capability (PMAX). As in the classic topology, the fMAX of the proposed amplifier circuit is reached when the output-device output capacitance furnishes all of the capacitance COUT, for a given combination of frequency, output power and DC supply voltage. It is also shown that numerical simulations agree well with theoretical predictions.
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      Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors
      • Author(s): V. Vescoli ; J.M. Park ; H. Enichlmair ; M. Knaipp ; G. Röhrer ; R. Minixhofer ; M. Schrems
      • Source: IET Circuits, Devices & Systems, Volume 2, Issue 3, p. 347 –353
      • DOI:  10.1049/iet-cds:20060374
      • Type: Article
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      • p. 347 –353 (7)
        With the continuing scaling of metal–oxide–semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps at the Si/SiO2 interface. In general, the large electric field is strongly localised in a well-defined region; therefore carrier injection and interface-trap creation are similarly concentrated. The strongly inharmonious characters of HC injection and resulting damage present a considerable challenge to both experimental and modelling efforts.The HC degradation behaviour of an n-channel LDMOS transistor is investigated under various stress conditions. By applying variable base charge pumping experiments, a consistent picture of the degradation mechanism can be depicted. HC-induced interface traps are generated in the channel region of the device, in the drift region below the thick field oxide and at the bird's beak edge. The latter is shown to dominate the degradation of Idlin, which is the most critical parameter concerning HC lifetime in this specific device.
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