Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 2, Issue 1, February 2008
Volumes & issues:
Volume 2, Issue 1
February 2008
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- Author(s): J. Hu and S. Sapatnekar
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, page: 1 –1
- DOI: 10.1049/iet-cds:20089003
- Type: Article
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- Author(s): H. Yao ; S. Sinha ; J. Xu ; C. Chiang ; Y. Cai ; X. Hong
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 2 –15
- DOI: 10.1049/iet-cds:20070190
- Type: Article
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As very large scale integration (VLSI) technology advances to smaller and smaller nodes, certain layout configurations tend to have reduced yield and/or reliability during manufacturing processes because of increased susceptibility to stress effects or poor tolerance to certain processes like lithography. Such layout configurations are called process-hotspots, which are represented here accurately and compactly by range patterns. The concept of a range pattern is introduced to represent a set of similar patterns compactly. Since low-yielding patterns are directly represented, it can supplement the deficiencies of available modelling and/or subsequent correction (for instance, mask synthesis) techniques. A scoring mechanism can be provided for each range pattern to score the problem regions covered by the range pattern according to their yield impact. A library of range patterns for representing the process-hotspots is being developed in collaboration with a semiconductor manufacturing company. A fast and accurate process-hotspot detection system based on the range pattern matching algorithm is implemented, which can find all occurrences of the process-hotspots represented as range patterns in a given industrial layout. Experimental results are quite promising and show that all the locations that match each range pattern (i.e. process-hotspots) in a given layout can be found in several minutes. - Author(s): A. Mitev ; M. Marefat ; D. Ma ; J.M. Wang
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 16 –22
- DOI: 10.1049/iet-cds:20070185
- Type: Article
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With semiconductor fabrication technologies that have scaled below 100 nm, the design–manufacturing interface becomes more and more complicated. The resultant process variability causes a number of issues in the new generation integrated circuit (IC) design. One of the biggest challenges is the enormous number of process-variation-related parameters. These parameters represent numerous local and global variations and pose a heavy burden in today's chip verification and design processes. A new way of reducing the statistical variations (which include both process parameters and design variables) according to their impacts on the overall circuit performance is proposed. The new approach creates an effective reduction subspace and provides a transformation matrix by using the mean and variance of the response surface. With the generated transformation matrix, the proposed method maps the original statistical variations to a smaller set of variables with which variability analysis is processed. Thus, the computational cost because of the number of variations is greatly reduced. Experimental results show that by using the new method, 20%–50% parameter reduction with only <5% error on average can be achieved. - Author(s): K. Cao and J. Hu
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 23 –29
- DOI: 10.1049/iet-cds:20070112
- Type: Article
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As VLSI technology scales towards 65 nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people often treat systematic components of the variations, which are generally traceable according to process models, in the same way as random variations in process corner-based methodologies. In particular, lithography-induced process variations are usually estimated by a universal worst-case value without considering their layout environment. Consequently, the process corner models based on such estimation are unnecessarily pessimistic. A new ASIC design methodology that captures lithography-induced polysilicon gate length variations including both the layout dependent systematic components and random components is proposed. This methodology also shows that lookup table methodology is sufficient to handle back end of line lithography process variations in timing analysis. In addition, a new technique of dummy poly insertion is suggested to shield inter-cell optical interferences. This technique together with standard cells characterised using the new methodology will let current design flows comprehend the variations almost without any changes. More importantly, by separating systematic lithography effect from random process variations, this methodology greatly reduces pessimism in timing analysis, thus enabling both aggressive design implementation and easier timing signoff. Experimental results on industrial designs indicate that the new methodology can averagely reduce timing variation window by 11% and power variation window by 55% when compared with a worst-case approach. - Author(s): X. Zhang ; L. He ; V. Gerousis ; L. Song ; C.-C. Teng
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 30 –36
- DOI: 10.1049/iet-cds:20070187
- Type: Article
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Chemical–mechanical planarisation (CMP) is an enabling technique to achieve wafer planarity in backend manufacturing processes of integrated circuits. However, CMP also causes variations in metal and dielectric thicknesses because of the non-uniformity of metal feature density. The authors first conducted a case study of CMP-induced variations using an industrial CMP simulator together with a widely used microprocessor hardcore fabricated in a 90 nm technology with eight metal layers and a system-on-chip design fabricated in a 65 nm technology with four metal layers. They revealed a few interesting characteristics on thickness variations and, particularly, vertical and horizontal correlations between variations, although such correlations have been virtually ignored by the existing study on layout optimisation. These characteristics may lead to better modelling and design optimisation for CMP variations. As an example, the authors then proposed a stochastic CMP model to efficiently incorporate CMP variations estimation in the design flow and developed two algorithms to reduce the CMP simulation runs by 7× and 3×, respectively, when compared with generating the stochastic CMP model by detailed CMP simulations.
Editorial: Design for manufacturability
Efficient range pattern matching algorithm for process-hotspot detection
Parameter reduction for variability analysis by slice inverse regression method
ASIC design flow considering lithography-induced effects
Case study and efficient modelling for variational chemical–mechanical planarisation
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- Author(s): Z. Ghassemlooy and M.D. Logothetis
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 37 –38
- DOI: 10.1049/iet-cds:20089001
- Type: Article
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- Author(s): W. Bziuk
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 39 –49
- DOI: 10.1049/iet-cds:20070101
- Type: Article
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A numerically efficient approximation for virtual partitioning, a scheme for connection admission control, is considered. It shares the resource among several traffic classes in a fair and efficient manner using a state-dependent trunk reservation. In the absence of a product form, an approximation for the occupancy distribution for this multirate loss system was originally suggested by Borst and Mitra. Based on this approximation, a more numerically efficient approximation is developed here. It combines asymptotic approximation methods with recursive formulas in a way that the computational complexity is reduced by several orders of magnitude. Furthermore, a modified approximation is derived such that its complexity scales independent of the state space. It avoids recursive formulas and thus is well suited for real-time computations, but with reduced accuracy. Numerical results show the computational efficiency of the new approximations and their accuracy is compared with the simulation results. It is clearly shown that this accuracy is comparable to that of the existing approximation methods. - Author(s): J.S. Vardakas ; M.K. Sidiropoulos ; M.D. Logothetis
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 50 –59
- DOI: 10.1049/iet-cds:20070047
- Type: Article
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The authors present an extensive investigation of the performance of the IEEE 802.11 medium access control (MAC) protocol, with respect to throughput and delay. For the protocol analysis, a new model, which describes the protocol's behaviour to a great extent by incorporating and extending the existing models, is proposed. The authors also present a detailed analysis of the end-to-end delay through the study of the MAC delay and the queueing delay. The authors use the Z-transform of backoff duration to obtain the mean value, the variance and the probability distribution of the MAC delay. For the queueing analysis, first the authors consider an M/G/1 queue in order to provide a first look at the queueing delay. Second, the authors modify the input process of the queue so that the packet arrival process is described by an ON–OFF model, which expresses the bursty nature of traffic. In the investigations, data rates of 1, 5.5 and 11 Mbps are assumed to highlight the effect of the bit rate on network performance for both Basic and request-to-send/clear-to-send access mechanisms. The throughput and delay analyses are validated by simulating the distributed coordination function, whereas the models are compared with the existing models based on their results. The accuracy of the analyses was found to be quite satisfactory. - Author(s): C. Chrysoulas ; E. Haleplidis ; G. Kostopoulos ; R. Haas ; S. Denazis ; O. Koufopavlou
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 60 –68
- DOI: 10.1049/iet-cds:20070041
- Type: Article
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Modelling is an essential tool in the development and assessment of new concepts. The authors propose an architecture for the next-generation gigabit distributed active router that was designed and implemented in the IST project, FlexiNET. In the FlexiNET project, a service called ‘dynamic service deployment’ dynamically installs, monitors and uninstalls new services on user demand or by default configuration. The proposed distributed router architecture achieves scalability of performance, functional flexibility and reliability. Scalability is achieved by adding new modules that have identical interfaces in an extensible function block. New services can easily be added by inserting modules that have the appropriate functionality. Another significant aspect of the model presented is that a failure in one module does not affect the other modules because they operate independently. - Author(s): I. Vasalos ; R.A. Carrasco ; W.L. Woo ; I. Soto
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 69 –79
- DOI: 10.1049/iet-cds:20070042
- Type: Article
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Nonlinear dynamic behaviour of transmission control protocol (TCP) in universal mobile telecommunications system (UMTS) networks is proposed. The dynamic characteristics of TCP are explored using the fundamentals of chaos theory, and the occurrence of chaotic behaviour in relation to the feedback that is received (packet drops, packet delays) by TCP from the network is explained theoritically. To validate the concept proposed, a model of the UMTS network is built and simulated under various user traffic loads. Using standard chaos methodology, it was found that inside the UMTS the TCP exhibits aperiodicity and sensitivity to initial conditions that are inherent characteristics of chaos. In particular, simulation results illustrate that as the traffic load increases, the behaviour of the network ranges from periodically stable to chaotic, with a direct impact on the quality of service of the network. - Author(s): M. Lunglmayr ; M. Krueger ; M. Huemer
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 81 –86
- DOI: 10.1049/iet-cds:20070040
- Type: Article
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The application of an equalisation method for mobile station terminals using particle filters is presented. To use particle filters for equalisation, a mathematical model is shown which allows the transmitted symbols to be represented as the state of a stochastic system, which can be estimated by particle filters. The authors propose an equaliser structure with particle filters for application in mobile station receivers, especially for GSM/EDGE (Global System for Mobile Communications/Enhanced Data Rate for GSM Evolution). Several improvement strategies, which help to obtain better estimation results with a lower number of particles, are discussed. In addition, performance evaluations of the particle filter equaliser for GSM/EDGE are presented. - Author(s): M. Gła˛bowski ; A. Kaliszan ; M. Stasiak
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 87 –94
- DOI: 10.1049/iet-cds:20070037
- Type: Article
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The paper proposes a new approximate calculation method of occupancy distribution and blocking probability in the full-availability group (FAG) with multi-rate traffic streams and bandwidth reservation. The algorithm involves calculation of system state probabilities by a convolution operation. In the paper, an effective method of calculating state probabilities in a reservation space of the system is derived. The analytical results of blocking probabilities in the FAG with bandwidth reservation, obtained on the basis of the proposed analytical method, are compared with the data obtained on the basis of other known analytical methods and with the simulation results. The accuracy of the proposed method is evaluated for different multi-rate Bernoulli (Erlang), Poisson (Engset), Pascal traffic streams. The method proposed is characterised by lower complexity than the convolution algorithm for the FAG with bandwidth reservation devised earlier. - Author(s): A. Al-Ka'bi ; M.E. Bialkowski ; J. Homer
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 95 –102
- DOI: 10.1049/iet-cds:20070032
- Type: Article
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A performance comparison between uniformly and non-uniformly spaced adaptive array antennas in a mobile fading environment is presented. Here, deterministic and simulation models of the frequency-non-selective mobile fading channels are investigated and used to explain the behaviour of steered beam adaptive arrays in terms of the output signal-to-interference-plus-noise ratio and pointing accuracy. It is found that the non-uniformly spaced arrays give a performance improvement of >25% in comparison with the uniformly spaced arrays. - Author(s): A. Saemi ; V. Meghdadi ; J.-P. Cances ; M.R. Zahabi
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 103 –111
- DOI: 10.1049/iet-cds:20070024
- Type: Article
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The maximum-likelihood (ML) time–frequency synchronisation algorithm combined with channel estimation for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems in frequency selective fading channels is addressed. In the proposed algorithm, the authors use two steps to maximise an ML metric to obtain first the frequency offset and then timing. A fast Fourier transform algorithm is used to estimate the frequency offset. Using these two estimates, the channel is identified. A simple iterative algorithm is proposed to improve the frequency offset estimation. The performance of the proposed synchronisation approach, in terms of timing failure probability and mean square error of the estimated frequency offset and bit error rate, is compared with others in the literature. Comparison of simulation results with the Cramer–Rao lower bound clearly illustrates the accuracy of the proposed algorithm, which outperforms the state-of-the-art synchroniser devices in the open literature. - Author(s): W.P. Ng ; W. Loedhammacakra ; Z. Ghassemlooy ; R.A. Cryan
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 112 –118
- DOI: 10.1049/iet-cds:20070238
- Type: Article
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The chromatic dispersion (CD) that occurs in single mode fibres (SMFs) is an important issue that needs to be addressed in long-haul optical communication links. The effect of CD is pulse spreading which in turn leads to inter-symbol interference, thus resulting in the deterioration of the bit error rate (BER) performance of the system. An alternative CD compensation technique that utilises a parallel optical all pass filter (p-OAPF) is presented, where the p-OAPF design is based on the inverse phase response of the SMF. The p-OAPF is based on a class of all-pass filter. Simulation results of the proposed technique show an increase in the repeater-less length of a point-to-point optical communication system by up to three and four times using a non-return-to-zero data format with a rectangular and Gaussian pulse shape, respectively, at error-free condition (BER<10−9). The results also show that the p-OAPF is robust in performing dispersion equalisation at a wide range of SMF lengths to attain error-free communication.
Editorial: Communication systems, networks and digital signal processing
Efficient computational technique for virtual partitioning
Performance behaviour of IEEE 802.11 distributed coordination function
Towards a service-enabled distributed router architecture
Nonlinear complex behaviour of TCP in UMTS networks and performance analysis
Feasibility study of particle filters for mobile station receivers
Asymmetric convolution algorithm for blocking probability calculation in full-availability group with bandwidth reservation
Performance of adaptive array antennas in mobile fading environment
Joint ML time–frequency synchronisation and channel estimation algorithm for MIMO-OFDM systems
Characterisation of a parallel optical all pass filter for chromatic dispersion equalisation in 10 Gb/s system
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- Author(s): M. Jamal Deen ; B. Bandyopadhyay ; Pradip Kumar Saha
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 121 –122
- DOI: 10.1049/iet-cds:20089002
- Type: Article
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- Author(s): S. Chandra ; A. Vishnu Vardhanan ; R. Gangopadhyay
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 123 –127
- DOI: 10.1049/iet-cds:20070145
- Type: Article
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Compensation of fibre dispersion-induced power fading in an externally modulated sub-carrier multiplexed radio-over-fibre transmission link using the chirped fibre Bragg grating (CFBG) has been investigated. The results show that periodic power fading caused by fibre chromatic dispersion is significantly reduced and the optimum transmission distance can be increased by proper design of grating parameters and optimum selection of apodisation profile. The investigation also reveals that carrier-to-noise ratio and bit-error rate of 156 Mbps DPSK signal are also significantly improved using the CFBG with asymmetric apodisation profile as the dispersion compensator. - Author(s): H.S. Dutta ; N.R. Das ; M.K. Das
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 128 –132
- DOI: 10.1049/iet-cds:20070141
- Type: Article
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The high-frequency performance of a Ge-on-Si resonant cavity encapsulated Schottky photodetector (PD) has been investigated. The normalised photocurrent has been calculated and computed considering the trapping of carriers at the Si/Ge hetero-interfaces. Results show that at low bias, bandwidth of the PD is controlled by the carrier-trapping effect at the hetero-interfaces and at high bias it is controlled by resonant-cavity effect and trapping-free transit-time effect. The PD design can be optimised for bandwidth maxima depending on the applied bias. - Author(s): Y.M.M. Antar
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 133 –138
- DOI: 10.1049/iet-cds:20070138
- Type: Article
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Over the last few years, developments in wireless communications have presented many challenges to the antenna and microwave communities in terms of special requirements for antenna design, fabrication and integration. These requirements include new characterisation in terms of antenna performance, miniaturised size and shape and new suitable fabrication and implementation techniques to fit with the devices. These aspects are addressed with a focus on recent developments in dielectric resonator antenna research to meet some of the new challenges. A few recent representative designs, which outline new innovations and improved antenna features, as well as directions for future research, are briefly described. - Author(s): A. Das Barman and P.K. Basu
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 139 –143
- DOI: 10.1049/iet-cds:20070129
- Type: Article
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139
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An analytical expression for power penalty (PP) from the formula for bit-error rate is derived by employing saddle point approximation in the chi-squared probability distribution function. This theory differs from the earlier ones in that it takes into account the dominant signal-amplified spontaneous emission beat noise applicable for optically pre-amplified systems. Imperfect extinction ratio accounting for higher power penalties is also considered in the analysis. Results have been compared with the available experimental results for a low number of crosstalk sources and an excellent agreement has been found. Although Gaussian probability density function (pdf) is simple to analyse, PP calculated from this pdf for a low number of crosstalk sources fails to match with the experimental results. - Author(s): S.K. Saha
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 144 –150
- DOI: 10.1049/iet-cds:20070126
- Type: Article
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A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source–drain engineering. An asymmetric channel doping profile along with ultra-shallow source–drain junctions was used to achieve the target drain programming voltage (Vsp) for an efficient cell programming while keeping the cell breakdown voltage, BV>Vsp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times. - Author(s): D. Vanhoenacker-Janvier ; M. El Kaamouchi ; M. Si Moussa
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 151 –157
- DOI: 10.1049/iet-cds:20070117
- Type: Article
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The silicon-on-insulator (SOI) CMOS technology is one of the best candidates for high-temperature applications due to its low leakage current, steep subthreshold slope, absence of latch-up phenomenon and temperature‐resistant threshold voltage. However, the most critical elements for high temperature applications are transmission lines, especially thin-film microstrip lines. In the paper, the impact of high-temperature operation on the RF performance of some SOI circuits is analysed up to 250°C. - Author(s): M.W. Shinwari ; M.J. Deen ; P. Selvaganapathy
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 158 –165
- DOI: 10.1049/iet-cds:20070162
- Type: Article
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The possibility of using devices based on field-effect principles for detecting DNA hybridisation events is an attractive and low-cost alternative to optical reading techniques. Experiments have shown that a change in the threshold voltage of a few millivolts can be attributed to successful hybridisation of targets to probe oligonucleotides tethered on the oxide of a field-effect transistor. Many different phenomena give rise to this voltage shift and some of these phenomena are described. Several justifiable approximations are made to develop an analytic solution of this biosensor that allow for a closed-form expression of the flatband voltage to be derived. Finally, a small-signal model for the BioFET is given, with emphasis on its design and operating conditions for optimum signal-to-noise ratio. - Author(s): S.R. Das ; A. Hossain ; S. Biswas ; E.M. Petriu
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 1, p. 166 –178
- DOI: 10.1049/iet-cds:20070119
- Type: Article
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The design of space-efficient support hardware for built-in self-testing is of immense significance in the synthesis of present day very large-scale integration circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). The authors revisit the general problem of designing zero-aliasing (or aliasing-free) space compression hardware in relation to embedded cores-based SOC for single stuck-line faults in particular, extending the well-known concepts of conventional switching theory and of incompatibility relation to generate maximal compatibility classes utilising graph theory concepts, based on optimal generalised sequence mergeability, as developed by them in earlier works. The authors briefly present the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test for realising maximum compaction ratio in the design, along with extensive simulation results on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM and COMPACTEST.
Editorial: Computers and devices for communication
Compensation of chromatic dispersion-induced power fading using optimised chirped fibre Bragg grating for millimetre-wave radio-over-fibre system
Frequency response of a resonant cavity encapsulated germanium-on-silicon Schottky photodiode
Antennas for wireless communication: recent advances using dielectric resonators
Incoherent in-band crosstalk induced power penalty in amplified WDM networks: a comparative study using Gaussian and chi-squared probability density functions
Scaling considerations for sub-90 nm split-gate flash memory cells
Silicon-on-insulator for high-temperature applications
Analytic modelling of biotransistors
Aliasing-free compaction revisited
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