To the best of the author's knowledge, several studies during 1960–2019 were carried out on wideband and ultrawideband LNAs just to render optimum LNAs for SAW‐less Radio‐Frequency Integrated Circuits (RFICs) but none of these works reviewed and taught the proceedings of these six decades, hence the lack of a comprehensive review is quite noticeable. This article specifically studies the challenges and solutions of designing UWB LNA by reviewing topologies and techniques such as inductive peaking, noise and distortion cancellation, g _m ‐boosting, active inductor and notch filter. Its historical aspect illustrates when the idea of wideband LNA was born and how it changed to ultrawideband LNA, and its tutorial aspect discusses circuits and achievements to present optimum LNAs in Complementary MOS (CMOS), BiCMOS and High‐Electron‐Mobility Transistor (HEMT) technologies. This work describes the endeavours of engineers in reaching UWB LNA from narrowband LNA during six decades that have great importance as a chapter in understanding this topic because it teaches all topologies, techniques, circuits and related events in a historical narrative for trained readers who are not experts on this topic.

This study presents a numerical analysis to correlate performance characteristics of indoor photovoltaic (PV) devices with those of DC‐to‐DC up‐converters designed for low‐power electronic applications. A theoretical model based on self‐consistent solution of Poisson's equation and continuity equation under optical generation‐recombination conditions has been applied to design Cu₂ZnSn(SSe)₄‐based PV devices having type‐I and type‐II energy band profiles, such that they can operate with peak efficiencies of 12.6% and 14.1%, respectively, under illumination from an experimentally characterized white light‐emitting diode. Each PV device has been subsequently utilized as the input source of a Meissner oscillator‐based self‐driven DC‐to‐DC converter. Comparative analysis shows that in spite of the lower PV conversion efficiency, the PV device having higher short‐circuit current density results in a higher output efficiency of the converter circuit. Similar characteristic trends are obtained for a boost converter operating in a discontinuous conduction mode, whereas a continuous conduction mode of operation results in the opposite trend. The underlying reason behind such an observation has been traced back to the transient behaviour of the inductor current of the converter. The results of this study suggest close correlation between physics‐based design parameters of the PV device and output performance characteristics of the converter circuit.

Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power time‐based DAC (T‐DAC) that fits low‐power low‐speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D‐PWM) signal through the DTC circuit, then converts this D‐PWM signal into an analogue voltage through the TVC circuit. This new T‐DAC is not only an energy‐efficient design but also an area‐efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse‐fine DTC circuit. Post‐layout simulations of the proposed T‐DAC is conducted using industrial hardware‐calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation.

The incorporation of Si_1−x Ge _x nanowire based metal‐semiconductor‐metal (MSM) Schottky biristor allows the conceptualization and realization of low latch‐up and latch‐down voltages with retained latching window. With the aim of investigating the device governing physics and device performance, mathematical simulation is carried out using exhaustive and calibrated 2D Technology computer‐aided design (TCAD) device simulation. The device performance is investigated with respect to channel doping, electrode work function, channel length, temperature and mole fraction (x) to maximize the latching window size and minimize the latch‐up voltage. The detailed sensitivity analysis is also carried for the proposed device with parametric sweep method.

A scheme to implement the Jerk form of the Chua system family using a controllable canonical form applied in linear systems is proposed. The main thought is that the nonlinear function with a single independent variable input can be superposed by a multiple linear function, which is regarded as the input of the system, and its single variable is regarded as the output of the system. Its state space could be reconstructed into the controllable canonical form. The output after transformation is fed back to the nonlinear function as its input independent variable, thus the controllable canonical form is transformed into the Jerk form of the Chua’s chaotic system. All Jerk forms of three‐order Chua system, and part Jerk forms of four‐order Chua system are presented. Analysis of the Lyapunov exponent spectrum, eigenvalues of the original three‐order, four‐order Chua systems and their Jerk forms, and the same values demonstrate the equivalent of the systems for both structures. According to the complexity and National Institute of Standards and Technology (NIST) test results, the pseudo‐random performance of the chaotic sequence brought by the Jerk forms of the Chua system is better. The simplest unified circuit block diagram for the Jerk forms of the Chua’s family is also given. By changing their resistance parameters, the bifurcation diagrams show that Jerk forms’ systems are entering chaos, these circuits implement results of 2–6 scroll attractors. Experimental observations are provided for confirmation.

The authors report experimental investigations on Hall sensors based on AlGaN/GaN heterojunctions grown on silicon 111 (Si 111) substrates. Realisation of two‐dimensional electron gas‐based Hall sensors on Si substrates can have the advantages of low cost and integrability with complementary metal‐oxide semiconductor circuits. Design and fabrication of such Hall sensors and their characterisation over a wide temperature range of 75 to 500 K are reported. The authors experimentally investigate the temperature dependence of the transresistances, sheet resistance and current‐related sensitivity (or gain) of such Hall sensors. The current‐related sensitivity is shown to be reasonably constant over the complete temperature range and certain inevitable variations in current‐related sensitivity can easily be compensated. The temperature dependence of the transresistance can be used for such compensation. The variation of the geometrical correction factor of the Hall sensor with the applied magnetic field strength and the operating temperature is also studied. The authors also demonstrate the possibility of realising Hall sensors with a high geometrical correction factor ( ≈0.97), which is practically insensitive to variations in temperature ( ≃2% from 75 to 500 K) and applied magnetic field, for applications such as in electromechanical devices.

As one of the most critical blocks of the CMOS image sensor (CIS), the accuracy and power consumption of the analogue‐to‐digital converter (ADC) play an important role in its performance. However, due to the mutually restrictive relationship between power consumption and accuracy in the single‐slope ADC (SS ADC), it is difficult to improve these performance indexes meantime without an efficient optimal design method. Here, an optimal design methodology based on an improved artificial fish swarm optimization algorithm (IAFSOA) is proposed for a 10‐bit SS ADC in CIS. First, a voltage storage structure and offset calibration circuit are developed for promoting the performance of the comparator. Then, IAFSOA is developed for the circuit parameters optimization with faster convergence rate and higher computational accuracy. The proposed multi‐objectives optimization algorithm can obtain the optimal parameters of the kernel circuit components and lead to an enhancement of both power consumption and accuracy. The optimized SS ADC is designed based on 0.18 µm process to verify the effectiveness of the proposed method. Compared to the earlier reported work, the IAFSOA‐based optimal design method can promote the performance of the SS ADC by an improvement of effective number of bits and a reduction of power consumption.

To obtain the required LED‐driving current, variable frequency control directly leads to large reactive circulation, and the design of the electromagnetic interference circuit is more complex. However, soft switching cannot be guaranteed by constant frequency operation under load variations. Hence, a multiplex LED‐dimming circuit based on a variable inductor is proposed that completes the constant frequency operation and realizes zero‐voltage switching to improve efficiency. The proposed circuit with a superimposed half‐bridge structure increases the number of outputs and simultaneously shares the resonant inductor so that the power density is improved and the LED‐dimming unit is simplified. The working principle of the circuit is described—it uses eight‐channel output to build an 80 W experimental prototype to verify the feasibility of the LED driver.

In most of the real time video processing applications, cameras are used to capture live video with embedded systems/Field Programmable Gate Arrays (FPGAs) to process and convert it into the suitable format supported by display devices. In such cases, the interface between the camera and display device plays a vital role with respect to the quality of the captured and displayed video, respectively. In this paper, we propose an efficient FPGA‐based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. The novelty of our work is the design of optimised architectures for Controllers, Converters, and several interfacing blocks to extract and process the video frames in real time efficiently. The flexibility of parallelism has been exploited in the design for Image Capture and Video Graphics Array (VGA) Generator blocks. The Display Data Channel Conversion block required for VGA to High Definition Multimedia Interface Conversion has been modified to suit our objective by using optimised Finite State Machine and Transition Minimiszed Differential Signalling Encoder through the use of simple logic architectures, respectively. The hardware utilization of the entire architecture is compared with the existing one which shows that the proposed architecture requires nearly 44% less hardware resources than the existing one.

This work presents a gallium nitride (GaN) high electron mobility transistor (HEMT)–based cascaded multistage power amplifier (MPA) in class‐AB for L‐band radar applications. The purpose of this endeavour is to develop an MPA using GaN HEMT devices to achieve optimised parameters such as high gain, high power, better efficiency, and linearity in a compact size. In an MPA design with multiple stages, oscillations are common owing to unwanted high gain at the lower frequency range. To overcome this issue, we introduced interstage harmonic termination networks as a novel approach to suppress high gain at low frequencies, which are prone to oscillations. The proposed cascaded MPA provides the maximum radio‐frequency output power of 89 W and a power gain of 52 dB with an associated power‐added efficiency of 51%. Second and third harmonic levels are −32.5 and −37 dBc, respectively. Two‐tone measurements are performed with a frequency separation of 10 MHz, and an intermodulation level of less than −33 dBc is achieved.

An energy‐efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross‐couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input‐referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.