Induction heating is regarded as a clean cooking technology, whose prominent advantages include contactless energy transfer, controllable heating rate, and safety. In household applications, it is expected that this approach is supposed to replace conventional gas stoves aiming at a more sustainable future. The increase of energy consumption associated with this trend cannot be neglected, while distributed generation (DG) stands out as a prominent solution to mitigate the impact on the power system. In this context, this work presents an induction heating system consisting of the integration of power electronic converters and a grid-connected photovoltaic (PV) system. Based on existing solutions available in the literature, it is possible to supply the induction stove with two distinct energy sources: the ac grid and PV modules. A high-voltage step-up dc–dc boost converter is employed to create a dc link responsible for connecting the PV system to the grid. The dc link is also used to supply a class DE parallel resonant inverter associated with the induction stove, which requires a low component count. Besides, the PV modules are capable of providing up to 3 kW under standard test conditions. Thus, part of the generated energy is used to supply the heating system, while the remaining portion is injected into the grid. Simulation results are presented to assess the performance of the whole system in steady-state and transient conditions, demonstrating that it is capable of operating at the maximum power point and injecting nearly sinusoidal currents with high power factor.

Lithium battery has become the main power source of new energy vehicles due to its high energy density and low self-discharge rate. In the actual use of the series battery pack, due to the internal resistance and self-discharge rate of batteries and other factors, inconsistencies between the individual cells are unavoidable. Such inconsistencies will reduce the energy utilisation rate and service life of the battery pack, and even endanger the safety of the battery systems. To improve the consistency of the series battery pack, a novel balancing method based on the flyback converter is proposed in this study. The flyback converter with a simple and reliable structure is used to realise the energy transfer between the whole battery pack and any single cell. Compared with the traditional balancing topology, the topology proposed in this study reduces the number of components and the volume of the balancing system, and only needs one set of control signals on the converter primary side, thus reducing the control difficulty. The experimental results show the effectiveness of the novel balancing method.

In this work, a frequency reconfigurable broadband radio frequency-predistorter (BB RF-PD) is proposed that can effectively suppress the power amplifier (PA) intermodulation distortion from 200 MHz to 2.5 GHz. It is an attractive lineariser solution for radio repeaters in long distance communication, where baseband information is not readily available. For broadband signals, existing linearisation techniques become intractable due to high cost and power consumption. The proposed BB RF-PD eliminates the use of data converters, field programmable gate arrays, but still provides the well-intentioned linearisation using the passive components. Three application scenarios have been investigated – (i) and (ii) intra-band: 160 MHz long-term evolution (LTE) signal and 100 MHz two-tone signal, and (iii) inter-/multi-band: two-component carrier LTE signal with frequency spacing of 1 GHz. For verification, the proposed BB RF-PD is implemented with a 10 W HMC8500 PA and tested using 160 MHz signal at 1.8 GHz. It delivers an adjacent channel power ratio (ACPR) of −45.65 dBc with an improvement of 16.87 dB, while for inter-band scenario a new technique has been devised for multiband communication, which is known as BB multipath RF-predistorter. It delivers an ACPR of −50 and −47 dBc for lower and upper CC, respectively.

A small-signal model is established for the basic constant voltage (CV) flyback converter firstly. Then the phase margin and the bandwidth, which can reflect the system stability and rapidity, are deduced through transfer function. The parameters affecting the stability of the system can be obtained by the model's derivation to confirm the appropriate external capacitance value. To improve the precision of CV, the compensation of cable is implemented through the module of irrigation current, pulling down the output voltage under any load conditions to the value of it with the maximal load. The prototype for the proposed CV converter has been fabricated in an MXIC 0.8 μm L80A1 process. The minimal static power consumption measured by a test is only 40 mW. In the CV mode, the precision of the output voltage can reach the level of ±1.5%. Therefore, the proposed control chip has a promising application in low power CV AC–DC flyback converter.

This study presents an all-digital power-efficient integrating frequency difference-to-digital converter (iFDDC) and explores its applications in gigahertz (GHz) frequency-locking. The iFDDC utilises a bi-directional gated delay line (BDGDL) to detect and accumulate the frequency difference between two GHz signals and digitises the result with ultra-low power consumption. The built-in integration of the iFDDC ensures that the in-band quantisation noise of the BDGDL and digital controlled oscillator (DCO) is first-order suppressed. The all-digital realisation of the iFDDC makes it fully compatible with technology scaling. The effectiveness of the proposed iFDDC is verified using the simulation results of a 5 GHz frequency-locked loop designed in a Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm 1.2 V complementary metal-oxide-semiconductor (CMOS). The iFDDC consumes only 474 µW, offering the lowest power/frequency efficiency among reported FDDCs. The DCO locks to 5 GHz reference in <10 cycles.

Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand multiplication to small operand multiplication, along with addition. The proposed design is synthesised with Xilinx ISE 14.4 software and realised using different field programmable gate array devices. The efficiency of the proposed design depends on combinational delay, area and power. Moreover, the new multiplier architecture achieves speed improvement over prior design.

In this work, the authors study the performance of black phosphorus double gate MOSFET (BP-DGMOSFET) within the ballistic limit. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) tool has been used for the first time to simulate the device characteristics. First, the density functional theory has been used to simulate the electrical characteristics of single and fewlayer (five layers) phosphorene (including armchair and zigzag directions). The parameters such as bandgap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the BP-DGMOSFET characteristics. They have used the kinetic velocity model and quantum model to account for the ballistic mobility and quantum effects in the device. The current drain characteristics are calibrated with non-equilibrium Greens function (NEGF) simulation and radio frequency (RF) characteristics with compact model values and found that their results agree with them. Secondly, the other RF figure of merits, such as maximum frequency of oscillation, transconductance, output conductance and stability has also been simulated. It is found that their proposed method shows results comparable to NEGF with reduced computation time and complexity.

In this work, a new fractional-order sinusoidal oscillator is proposed. The proposed oscillator consists of one fractional-order all-pass filter and one fractional-order lossless integrator blocks. In order to emulate fractional-order capacitors, three different approximation methods the R–C pair, Matsuda and Oustaloup are employed and the results are compared. Three sinusoidal voltage signals with different phases that are controlled by fractional orders are provided by the proposed oscillator topology that is not possible for the classical integer-order case. Grounded passive components are used in the introduced oscillator circuit. Additionally, the output voltage signals are available at the low impedance terminal W of AD844ANs. Moreover, the time constant of the fractional-order all-pass filter can be adjusted accurately by means of second resistor R _x in the all-pass filter section. In addition to the simulation results, the proposed fractional oscillator is also implemented to verify the oscillator circuit experimentally. For the case of fractional orders α = 1 and β = 0.5, the measurement results are 10.3 kHz, 43.22° and 67.99°, respectively, while the desired values are 10 kHz, 45° and 67.36°, respectively.

Accelerators that utilise the sparsity of both activation data and network structure of convolutional neural networks (CNNs) have demonstrated efficient processing of CNNs with superior performance. Previous research studies have shown three critical design concerns when designing accelerators for sparse CNNs, including data reuse, parallel computing performance, and effective sparse computation. These factors were each used in the previous accelerator designs, but none of the designs have considered all the factors at the same time. This study provides analytical approaches and experimental results to reveal the insight of accelerator design for sparse CNNs. The authors have shown that the architectural aspects need to be all considered to avoid performance pitfalls, including their mutual effects. Based on the proposed analytical approach, they proposed enhancement techniques and co-designed among the factors discussed in this study. The improved architecture shows up to 1.5× data reuse and/or 1.55× performance improvement in comparison with state-of-the-art sparse CNN accelerators while still maintaining equal area and energy cost.

This study proposes an analytical drain model of the strained junctionless nanowire tunnel field-effect transistor fabricated on the virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the virtual substrate. An analytical expression for the drain current is derived by using the tangent line approximation method. The strain induced in the device could reduce the effective tunnelling barrier significantly, resulting in a larger band-to-band tunnelling generation rate and, therefore, higher drive current compared with the unstrained device. Impacts of device parameters such as the channel diameter, gate oxide thickness and gate dielectric constant on the device performance are investigated. Results of the proposed model are verified by comparing with the device simulator.

Asynchronous quasi-delay-insensitive (QDI) circuits have recently become an active research area in digital logic design. In contrast with synchronous paradigms, QDI approaches utilise threshold gates with hysteresis, such as Muller C-element and null convention logic (NCL) gates. However, there are no existing methods to explicitly describe these hysteretic logic gates in Boolean algebra. Therefore, in this study, the authors extend the Boolean algebra with two novel operators, named completion and truth tuple, to enable explicit expressions for all QDI elements such as C-elements, NCL, NCL+, latches and several non-conventional hysteretic threshold gates that they call dual-threshold logic. In addition, they develop a set of 16 laws and theorems for these new operators to create a complete novel algebraic extension for QDI logic. It is demonstrated that the authors' extended algebra is a complete approach for explicit design and analysis of QDI circuits, including logic description, equation formation from truth table, expression simplification and conversion, and even gate mapping and corresponding CMOS implementation. They also provide an analysis and solution for netlist corruption problems during the synthesis process of existing QDI design flows, as well as a complete design example using the extended Boolean algebra with different QDI design styles.

This study presents a novel high gain operational amplifier (op-amp) and a comparator using n-type all enhancement amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The proposed op-amp employs regulated cascode topology in conjunction with capacitive bootstrap load, which enhances the gain to 159.87% (V/V) as compared to op-amp with bootstrapping load. In addition, common mode feedback is introduced in the circuit which improves the common-mode rejection ratio (CMRR) of the amplifier without hampering the output voltage swing. The proposed op-amp offers a voltage gain of 46.2 dB, phase margin of 67°, CMRR of 51.8 dB, unity gain frequency of 215 kHz and power consumption of 0.22 mW. Furthermore, a novel comparator circuit at a clock frequency of 50 kHz is reported. The power consumption of the circuit is 0.248 mW and it can discriminate a minimum voltage of 50 mV. The performance of the proposed circuits is demonstrated using an analytical model of a-IGZO in Cadence environment with a channel length of 20 µm at a supply voltage of 10 V. Further with the help of the circuits reported in this work, many sensing systems of practical importance can be developed, such as smart packaging and bio-medical wearable devices using flexible electronics.

This study deals with a single soft fault diagnosis of non-linear circuits having multiple DC solutions. The key problem of the diagnosis is arranging a measurement test. Creation of the test for the above-defined class of circuits is discussed in detail. It is assumed that only input and output terminals are accessible in the circuit. The test is created based on some single-valued input or transfer characteristics traced in a modified circuit. The modification does not disturb the integrity of the circuit and is realised by connecting some components to the accessible terminals. A very fast method for tracing the characteristics is developed. Having appropriate characteristics several values of the exciting voltage are chosen and the corresponding values of voltage or current defined by the characteristic are measured in the course of testing. The method for arranging the measurement test is illustrated using four non-linear circuits having multiple DC solutions and three of them were built in bipolar and complementary metal-oxide-semiconductor (CMOS) technology. One of the circuits is comprehensibly diagnosed using a method for detecting, locating, and estimating values of different faulty parameters exploiting the proposed test.

This study presents the performance of differential cascode balun low noise amplifier (DCBLNA) with ultra-wideband (UWB) for human breast cancer diagnosis. The proposed DCBLNA design-I with bulky spiral inductors achieves insufficient bandwidth with large power consumption of 10.8 mW. To attain the proper UWB band of operation, suspended strip line (SSLIN) radiators have employed in the proposed design-I. The performance of SSLIN is evaluated in terms of line capacitance and characteristic impedance by optimising its width. It is observed that best 50 Ωn-II. DCBLNA design-II using SSLIN have achieving a desired band of operation ranging from 1.5 to 15.7 GHz and best NF of 0.5 dB. The gain and phase imperfections are simulated to characterise balun networks. The smallest gain imperfection achieved is 0.1 dB at 10 GHz while the simulated phase imperfection turns out to be sufficiently good with 2.35° at 8 GHz. The proposed DCBLNA design-II is implemented and fabricated using RFCMOS 45 nm Taiwan Semiconductor Manufacturing Company (TSMC) process under commercial conditions. The highest figure of merit comes out to be 3.2 that ensures good accuracy of medical imaging for breast cancer diagnosis.

In this study, the design routine of a novel phase frequency detector and charge-pump (PFD-CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD-CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast-locking low-power phase-locked loop (PLL) has been implemented which can operate at the range of 100 MHz–1.2 GHz while its power consumption is 2.53 mW at 1.2 GHz operating frequency. The whole PLL is implemented in 0.18 µm complementary metal–oxide–semiconductor technology with a 1.8 V power supply. The post-layout simulation results are provided to show the conformity of theoretical assumptions and circuit-level implementations which depict the locking time of 0.54 µs at 1.2 GHz operating frequency.

In this study, a method for fine adjustment of Xilinx field programmable gate array (FPGA) routing delays is proposed and applied to improve the linearity of an unbalanced multi-measurement time-to-digital converter (TDC). The delay control method increases load capacitances of interconnect points of switch matrices by small amounts using additional connections to unused interconnects in the FPGA fabric. The novel delay control method uses the tool command language (TCL) scripting feature available in the Xilinx Vivado tool to automatically add wires into a fully placed and routed design. A total of 61 additional wires were successfully and automatically added to reduce the differential and integral non-linearities of the target TDC from 0.51 and −0.54 LSB to 0.05 and 0.06 LSB, respectively (reduction factors of 10.2 and 9) for an LSB equal to 333 ps.

The increasing demand for high-performance computing has emphasised the invocation of sophisticated multi/many-core computing architecture. Graphical Processing Unit (GPU) is considered to be an essential innovation in this regard as GPU offers a significant amount of parallelism in the execution of complex computing applications. The performance of GPUs in reducing the computational time of such applications is worth mentioning. Although GPUs appear to be a problem-solving solution for complex applications yet high power consumption has been a challenging problem, associated with this many-core computer architecture. Efficient resource management is a emerging and promising solution to this challenge; however, reducing the resources would degrade the system's overall performance. On the other hand, reducing the resources based on the analysis of workload can save significant power without degrading the system's overall performance. Therefore, a smart controller to optimise the resources of general purpose-GPU (GP-GPU) architecture is required. AFBRMC-2, a neuro-fuzzy type-2 based controller, is presented for GP-GPU architecture and, based on a feedback mechanism, keeps analysing the stats of processor and manages resources using dynamic voltage frequency scaling and core gating techniques. The proposed controller achieved up to 55% reduction in power consumption against various benchmarks on the NVIDIA TK1 GPU kit.

Recently, the wireless sensor networks have rapidly emerged into agriculture and greenhouse because of owing many advantages than the traditional methods. However, some subjects such as cost and power are being brought up as a controversial issue. This study presents a developed wireless sensor network based on a proposed algorithm to improve tomato crop in a greenhouse. The developed sensor nodes, which own low-power consumption and also low-cost, monitor parameters like temperature, humidity, CO, and light intensity. The users define the minimum and maximum setpoints for the sensors to make an appropriate condition in the greenhouse. Also, the developed system was equipped with irrigation management that works based on time and date that maintain optimum water in the soil. The obtained results reveal that the amount of the tomato crops increases 30% than traditional methods after benefiting the developed system as well as the greenhouse experiences a decrease in consuming methane gas, water, and electricity as 30, 24 and 10% separately, in comparison to the traditional methods.

Electrical tuning of bandwidth is critical for microelectromechanical system (MEMS) resonator-based narrowband filters especially at ultra-high frequency ranges and beyond. The resonance frequency of MEMS resonators is highly susceptible to fabrication process uncertainties and very small fabrication variations could result in significant shift in their resonance frequency. Although, disk resonators are the most acceptable candidates for implementing of resonators at GHz frequencies, according to their high stiffness, electrical tuning of these resonators and consequently the resulting filters is almost impossible. This study presents a novel tuning method for low velocity through anchor coupled MEMS radial contour mode disk resonators based on the coupling beam's stiffness tuning using the piezoelectric effect. As the results of this method, high bandwidth tuning ratio as 1:1.25 is achieved due to changing the tuning DC voltage from 0 to 20 V. This impressive result for a narrowband filter with 450 kHz of bandwidth is achieved due to changing the stiffness of low stiff coupling beam which is much easier to control in comparison with extremely high stiffness disk resonators. Various simulation results, as well as analytical works, verify the proposed approach.

The study discusses selected issues of modelling and designing current-mode devices. The authors propose the design flow that covers abstract behavioural models, the schematic and SPICE-level netlists and the post-layout parasitic parameters. The considerations related to the analogue functional blocks with a dual-stage complexity. The theoretical backgrounds of the current-mode basic building blocks are introduced. Special attention has been paid to a new current-mode active component, digitally programmable modified current differencing transconductance amplifier (MCDTA). Based on the idea of an MCDTA, the authors have developed their own cell, which integrates the digital control feature (programmability) into current-mode analogue devices. This original solution enables the dual control techniques, coarse digital control and precise analogue control to be used. The presented examples of continuous-time active filters show that such a solution enables flexibility in the digital control of the parameters of analogue blocks. In order to facilitate the integration of the analogue and mixed-signal models in a single environment, VHSIC Hardware Description Language - Analogue Mixed Signal (VHDL-AMS) language was selected for the behavioural modelling methodology. The authors have used the back annotating mechanism to update behavioural models based on an estimation of the post-layout parameters. The approach is presented on examples that were implemented in TMSC 40 nm complementary metal–oxide–semiconductor technology.

A novel double-trench superjunction SiC metal–oxide–semiconductor field-effect transistor (MOSFET) with an integrated Schottky contact at the drain side is proposed in this study. Results indicate an improvement of 58% in reverse recovery current /charge and 22% in the trench corner electric field compared to the device without Schottky and without superjunction, respectively. This comparison became possible using mixed mode simulations in Sentaurus TCAD. While the improvement in electric field is due to incorporation of superjunction concept along the drift region, the improvement of reverse recovery is due to Schottky contact forming a barrier for the charge carriers. Using calibrated two-dimensional numerical simulations, the authors were able to demonstrate the influence of Schottky contact on reverse recovery current of the device. The superiority of the proposed device is presented by plotting the switching energy loss with respect to external gate resistance and temperature through non-isothermal simulations.

A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current (I _ON) and the threshold voltage (V _th) variation. Sub-threshold regime has been considered here to detect the charged/neutral biomolecules. Extensive simulations have been done using the SILVACO ATLAS. Sensitivity analysis has been carried out by considering half-filled and full-filled nanogaps with the neutral or charged biomolecules inside the cavity. Significant sensitivity and excellent reduction in short-channel effects has been observed in proposed biosensor.

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel-metal-oxide-semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is completed by two identical PT compensation bias voltage generators (PTCBVGs), which can guarantee the designed transconductor high tolerance for PT variations. A complete CMOS transconductor with PTCBVG has been designed and simulated using 0.18 μm technology. The effectiveness of PT compensation technique is proved. The simulation results of post-layout are commensurate with pre-layout. Post-layout simulation results show that when temperature changes from − 40 to 85°C for different process corners (TT, SS, SF, FS and FF), the transconductance varies from 91.8 to 123.6 μS, the temperature coefficient is <1090 ppm/°C, the total harmonic distortion is from  − 78 to −72dB at 1 MHz for 0.2 V_PP input signal, −3 dB bandwidth changes from 2.5 to 5 GHz, input-referred noise varies from 78.1 to 124.8 nV/sqartHz at 1 MHz and DC power is from 1.5 to 3.2 mW.

Approximate computing provides a promising way to achieve low power design at the cost of acceptable error. As a core component in a processor, the performance of the multiplier is important. This study presents designs of approximate-truncated Booth multipliers (ATBMs) using proposed approximate modified radix-4 Booth encoders (AMBEs), approximate 4-2 compressors (ACs) and gradually truncated partial products. The accuracy of the ATBMs is adjustable with the so-called approximation factors that indicate the number of AMBEs and ACs used. The normalised mean error distance and the product of the power and delay are used to evaluate the error and the hardware performance of the multipliers. The results show that the proposed ATBMs outperform previous approximate Booth multipliers. Their validity is also shown with case studies of image processing, K-means clustering and handwritten digit recognition.

Approximate computing is a novel approach to design area-efficient arithmetic units for portable error resilient applications. In this work, the authors have proposed a parallel architecture for median filter targeting digital image processing. Proposed parallel median filter (PMF) uses pre-sorter and post-merge units to replace corrupted processing pixel (PP) with a median of pixels in the 3X3 processing window. Approximate compare and swap (CS) blocks that can trade off area at the expense of accuracy are proposed and used in the proposed PMF. Two variants of PMF are realised based on the implementation of approximate CS units in the pre-sorter and post-merge blocks. In PMF-design1, the authors use the exact CS unit in the pre-sorter and approximate CS unit in the post-merge block (hereafter referred to as P-EA) and in PMF-design2, they use approximate CS unit in both pre-sorter and post-merge blocks (hereafter referred to as P-AA). Functionality and accuracy efficacy of the proposed PMFs are verified with the image de-noising application. Synthesis with 90 nm application specific integrated chip technology revealed that to the least, proposed PMFs demonstrate 33.75 and 41.9% area-delay product and power-delay product reductions, respectively, compared to the standard median filter.