Ternary content addressable memory (TCAM) is a high-speed memory employed in network search engines which consume significant power. Many authors have provided efficient power solutions by proposing different match line schemes. This study proposes the use of energy recovering adiabatic logic scheme in the design of power-efficient TCAM. Two different innovative quasi-adiabatic TCAM (QATCAM) core cells are designed. The design is implemented in 180 nm complementary metal-oxide semiconductor technology with a power clock of 1.8 V on Cadence Virtuoso. It is found that the power dissipated by the proposed QATCAM cells is lower than its conventional counterparts. Adiabatic TCAM arrays are designed using adiabatic peripheral circuits. The proposed adiabatic TCAM core cells yield more considerable power savings even at higher frequencies up to 1 GHz.

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.

This study presents a low-cost multi-throughput true random number generator (TRNG) intellectual property (IP) based on a variable-length multi-mode ring oscillator. The proposed TRNG implements a multi-throughput feature by bypassing inverter cells in the ring oscillator for reducing the loop delay. This multi-throughput feature offers the advantage of high-performance or low-power operation when needed. These options make the proposed TRNG suitable for end-to-end encryption in highly restricted devices such as Internet of Things sensor nodes. Measurement results show that the proposed TRNG passes national institute of standards and technology (NIST) tests for different throughput operations. The TRNG is embedded in a reduced instruction set computer V (RISC-V)-based system-on-chip (SoC) for periodical-driven applications, and it achieves an energy efficiency of 92 pJ at 3.7 Mbps, occupying in a 180 nm technology. This study also presents a system technique to implement the entropy enhanced TRNGs, using multiple entropy sources. An extraction system provides high-quality random numbers with a sampling method that takes one entropy output to sample the other entropy sources. The system requires few resources, using low-cost TRNG IPs as entropy sources.

Open-circuit voltage decay (OCVD) is a method to characterise minority carrier effective lifetime (). It is non-destructive, simple and low-cost. It has been mainly used in silicon p-n junctions. is not only a very important parameter to optimise device design but also to supervise process steps. It is not the only parameter we can obtain by OCVD. Due to the intrinsic space charge region capacitance of a p-n junction, the doping level of the lowest-doped region () and built-in potential () are extractable. Moreover, it is also possible to obtain the shunt resistance () value when it has a significant effect on the p-n junction behaviour. The authors first applied the well-established one-diode model in a transient regime to simulate OCVD signal. In a second step, they used an optimisation algorithm to fit the experimental curve of a silicon diode to extract , , and . These values were compared to those obtained from C–V and I–V. Results are promising and demonstrate for the first time, the flexibility of the OCVD method. It opens up the perspective for the development of add-on features of the method and for measuring short lifetime.

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance over the whole operating band is significantly reduced by applying the multifinger layout technique and employing shunt passive elements for the input device without degenerating the structure, respectively. As part of the proposed SNIM method, a two-dimensional contour plot-based process variation tolerant bias voltage set up protocol is developed which can optimise forward gain (S ₂₁), noise figure (NF) and stability factor simultaneously. The regulation of amplifier port parameters with bias settling contour plots and finger parameters results in the proposed SNIM technique. For the CG-input-matched LNA, the post-layout electromagnetic simulated NF is between 3.08 and 4.1 dB, the average power gain of 25.52 dB with a power consumption of 20.19 mW and the CS-input-matched LNA achieves an NF in between 2.772 and 3.04 dB, the average power gain of 17.98 dB while the dissipated power is 20.73 mW.

This study reports an analysis of noise figures (NFs) in a reflection-type microwave amplifier using resonant tunnelling diodes (RTDs). The minimum NF for the RTD amplifier based on 0.9 μm InP process technology, featuring a power gain (S ₂₁) of 10.4 dB and a dc-power consumption of 133 μW at a centre frequency of 5.7 GHz, is measured to be 5.08 dB at a bias voltage of 0.355 V. The estimated NF characteristic based on an equation of the noise factor caused by the shot noise (F _SH) and a simulation of the noise factor generated by the thermal noise (F _TH) closely matches the measured NF characteristic, in the high-gain bias range of 0.32–0.38 V and near the centre frequency. It is found that the measured NF value of 5.08 dB originates mostly from the F _SH of 1.88 and the F _TH of 2.02. Additionally, the effect of the RTD parameters on the achieved NF is investigated, indicating that the negative resistance (R _D) magnitude had a dominant effect on the NF by changing the F _TH as well as the F _SH.

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Electronic systems’ growth causes complexity and increases the risk of failure. Fault tolerance structures are one of the useful ideas for resolving this problem. In this paper, a fault tolerant approach to digital electronic modules is introduced, using hardware redundancy to make those modules fault tolerant. The proposed structure of hardware redundancy has a voter unit that can mask and detect faults at the same time. Such a voter unit is achieved by using both majority voter units and minority voter units in its structure. The proposed voter unit has a three-layer structure. One minority voter, three majority voters, and another minority voter are respectively producing these three layers of the proposed voter unit. These layers can mask and correct fault and detect the faulty module by producing a unique fault detecting code simultaneously. The code works properly as long as the majority of the modules work properly. Then, the result of the voter unit (the code) is transmitted to a relevant switching unit in order to switch the faulty module with a spare module. A redundant system based on the proposed redundancy structure with M spare modules can switch M faulty modules and tolerate (M + 1) faults.

In a recent work on multiple constant multiplication (MCM) problems, a fully predictable sub-linear runtime heuristic was introduced, called Radix-2 ^r MCM. This method shows competitive results in speed, power and area, comparatively with the leading algorithms. In this study, the authors combine Radix-2 ^r MCM with an exact common subexpression elimination (CSE) algorithm. The resulting algorithm denoted Radix-2 ^r -CSE allows a substantial reduction in the number of addition/subtraction operations in MCM by maximising the sharing of partial terms after an initial recoding in Radix-2 ^r MCM. The savings over Radix-2 ^r MCM ranges from 4.34 to 18.75% (10% on average) when considering a set of 14 benchmark finite impulse response filters of varying complexity.

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an efficient FFT architecture in this study. Each and every state of the FFT stores the input and output the data using the R2DIF method. Also, the complex twiddle factors in FFT are replaced by the proposed uniform Montgomery algorithm. This technique simply performs the shift-add method instead of the multiplication process which also enhances the convergence of the calculation. So, the FFT implementation is done with the help of the proposed method which reduces the usage of chips in the process. Based on this approach, it performs the operation of FFT from 16 points to 1024 points and the performance of this proposed method is compared with existing approaches. Moreover, it does not require expensive dedicated functional blocks and uses only distributed logic resources. The simulation is carried out by the Xilinx platform using Verilog coding. The proposed design outperforms conventional methods in terms of less usage power and high speed.

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.

Radio frequency (RF) coaxial connectors are important constituents of modern communication systems. The degraded electrical contacts may adversely affect the signal transmission efficiency particularly in the case of loose connections. In this study, a distributed equivalent model of a coaxial connector with degraded receptacle and the loose connection was developed. The scattering parameters were analysed from the perspectives of both experimental testing and model simulation. The equivalent model and experimental results show good agreement. The impact of the degraded receptacle and loose connection on signal integrity was studied along with its electrical performance repeatability for different cases with respect to a degraded and loose connector. In addition, for the same degradation and loose level, the variation of contact resistance and contact capacitance was also investigated. These results are helpful for a better understanding of the intermittent failure of RF connectors. Moreover, these conclusions are also useful for diagnosing circuit faults caused by deteriorated repeatability of degraded and loose connectors.

In this study, a 60 nm gate length double-gate AlGaN/GaN/AlGaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed and different electrical characteristics, such as DC, small-signal, radio-frequency (RF) and high-frequency noise performances of the devices are characterised through TCAD device simulations. The results of double-gate MOS-HEMT are compared with the TCAD simulation results as well as with available experimental data of single-gate AlGaN/GaN MOS-HEMT having a similar gate length available from the literature. It is observed that the double-gate AlGaN/GaN/AlGaN MOS-HEMT shows good sub-threshold slope, improved ON current, short-channel effect immunity, improved RF and noise performance. A look-up table-based Verilog-A model is developed for both devices and the models are incorporated into the Cadence EDA tool to utilise the proposed device in circuit simulations. The Verilog-A model is applied to design a 1–20 GHz wideband feedback cascode low-noise amplifier (LNA). Performance variability of LNA due to single- and double-gate MOS-HEMT is also investigated.

In this paper, we have designed and realized a two-stage low-noise power amplifier (LNPA) with resistive feedback network targeting for Ka-band compact RF front-end applications. Featuring the characteristics of both low noise and high power at the same time, the LNPA is expected to be a possible one-chip replacement of power and low noise amplifiers integrated in a conventional transceiver/receiver (T/R) module. Such configuration features size compactness while reduces implementation complexity which is of crucial importance for integration in antenna arrays with large number of antenna elements. Implemented in 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology, the LNPA, operating at 36–40 GHz, exhibits a peak gain of 15.96 dB, a minimum noise figure of 2.88 dB, a power consumption of 152 mW and a measured 1-dB compression output power of 14.92 dBm at 38 GHz, respectively. The LNPA also featured a very good linearity performance with a measured output third-order interception point (IP3) of 22.22 dBm at 38 GHz.

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length which depends on tunnel current and does not depend along a transverse direction within the channel. The model is valid for the whole device structure rather than just semiconductor/insulator interfaces. The impact of variation of bias condition on channel potential is also investigated in the sub-threshold region. Finally, drain current is evaluated using Kane's and Kleysh's model and validated with a calibrated simulation, which has been carried out using 2D TCAD Sentaurus simulator.

Mathematical modelling of non-linearity due to charge injection phenomenon with variation in desired characteristics of complementary metal oxide semiconductor (CMOS) image sensor (CIS) and correlated double sampling (CDS) circuits is presented. Existing suppression strategies of charge injection effect for CIS and CDS circuits lack in accuracy because of the absence of knowledge of its effect with variation in major device parameters related to switching transistors viz. width (W), length (L), sense node capacitance (C_pd ) and photon current (I _ph). Therefore, variations in these parameters under the effect of charge injection have been experimentally studied. Based on the outcomes, it can be concluded that four-parameter logistic regression symmetrical sigmoid function is the best fit for the non-linearity introduced. Also, the devised mathematical model could be utilised as an activation function to train the biological neurons in CIS centred biomedical applications. A brief illustration of the same has been included for electrical stimulation of retinal cells. Further, the higher values of I _ph, C_pd and scaling of switching transistors as W _min and L > L _min can prove effective in reducing the non-linearity. Contrary to previous studies, the higher value of C_pd utilising the normal photodiode found suitable for charge injection suppression in CIS.

In recent past, the cross-coupling crosstalk becomes a dominating factor due to the closer proximity of wire that reduces the performance of coupled interconnects at lower technology. To overwhelm interconnect problems, this work demonstrates a comprehensive study of unshielded and active shielded spatially arranged mixed carbon nanotube (CNT) bundle (SMCB) and randomly distributed mixed CNT bundle (RMCB) interconnects at 10 nm technology. Using a driver-interconnect-load setup, a unique multi-conductor transmission line and an equivalent single conductor model is proposed considering the impact of different CNT diameters with their associated line and coupling parasitics. A resistive and CNT field-effect transistor (CNTFET) driver model is considered at 10 nm technology to demonstrate the impact of single line delay, cross-coupling delay, and power dissipation for the densely packed bundle at global lengths. It is observed that a CNTFET-based realistic RMCB exhibits on an average 29.19 and 39.56% reduced single line delay and power dissipation, respectively compared to different SMCB configurations at 700 µm interconnect lengths. Moreover, a shielded RMCB encouragingly provides an improved immunity of cross-coupling impact for the on-chip interconnects at 10 nm technology. Therefore, from fabrication and modelling aspects, a randomly distributed MCB can be proved as emerging interconnect for next-generation on-chip applications.

In this work, the authors demonstrate the realisation of metal controlled (MC) dopingless (DL) metal oxide semiconductor field-effect transistor (MOSFET) on a selective buried oxide (SELBOX). The different doped regions of the proposed device, such as source/drain and metal partial ground plane, have been realised with different metal work functions and the device is being named as MC-DL-SELBOX-MOSFET. A 2D simulation studies have shown MC-DL-SELBOX-MOSFET can outperform the conventionally doped SELBOX-MOSFET (D-SELBOX-MOSFET) in terms of short channel performance comparison. The severity of short channel effects is significantly less in MC-DL-SELBOX-MOSFET than D-SELBOX-MOSFET and most importantly the proposed device can be scaled below 10 nm without degrading the performance. Further, the ac analysis has shown that transconductance and cut-off frequency of the MC-DL-SELBOX-MOSFET are higher than D-SELBOX-MOSFET. Besides this, MC-DL-SELBOX-MOSFET is unhampered from the doping-related complications and can be processed at low temperatures.

This study presents two configurations to realise the behaviour of a floating memristor and an inverse memristor. The modified version of VDCC (voltage differencing current conveyor) termed as MVDCC (modified VDCC) is used to develop the presented emulators. The floating memristor emulator uses a single MVDCC and two grounded passive elements while the configuration of floating inverse memristor emulator is based on two MVDCCs, two grounded resistances and single grounded capacitance. The behaviour of both the circuits can be controlled through applied bias voltage as well as the employed grounded resistances. Both the presented circuits do not employ any external analogue multiplier circuit/IC, which can be considered as the most notable feature of these circuits. This study also describes the mathematical properties of memristor and inverse memristor taking both symmetrical and non-symmetrical models into account. PSPICE simulation tool is used to verify the working of realised emulation circuits using 0.18 μm CMOS process technology. The implementations of realised emulators, employing commercial ICs like AD844, CA3080 and LM13700, have also been presented and validated.

Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS-based ternary logic gates and unary operators are reported using static diode voltage divider topology. The main focus of the proposed ternary designs using DCVS logic style is to provide minimum energy consumption with less area overhead. In the presented method, a new power efficient and compact solution is being provided to improve the driving capability of the ternary DCVS circuits. All the simulations are performed on HSPICE synopsis simulator using 32 nm technology under different operational conditions. For the inversion and logical operations, the proposed method has a maximum power reduction of 45% and an energy reduction of 30% as compared to earlier reported DCVS designs. In the case of shifting operators, the maximum power reduction of 38.93% and an energy reduction of 39% are achieved. The design performance is robust when subjected to various process variation effects and have sufficient noise margins.

This study proposes a design of a maximum power point tracking (MPPT)-based DC–DC boost converter for an radio frequency (RF) energy harvester. The MPPT technique has been implemented in the converter using an adaptable load tracking mechanism with variable input RF power to meet the supply voltage tolerance limits. The proposed MPPT scheme is implemented using a sample-and-hold circuit in the tracking loop of the DC–DC boost converter. The complete energy harvester system prototype has been realised in a 130 nm standard complementary metal-oxide-semiconductor (CMOS) process. The footprint of the proposed converter circuit is much smaller compared to similar designs reported in the literature making it applicable for wearable and implantable biomedical applications.

One selector-one resistor (1S-1R) configuration is desirable to use in conductive bridge resistive random-access memory (CBRAM) and resistive random-access memory (RRAM) crossbar arrays (CBAs) to reduce sneak path current. In this study, an analytical model of Ta2O5/TaOx/TiO2 selector device is developed and is integrated with RRAM model to demonstrate the acquired features of 1S-1R to reduce the sneak path current. The proposed selector model is developed by considering the electric field-driven tunnelling mechanisms co-exist in thin multi-layer devices such as direct and Fowler-Nordheim tunnelling. The simulated characteristics of proposed model shows high non-linearity (∼1600), high selectivity (∼10⁴), high current density (∼10⁷ A/cm²) and low off current (∼46 nA). Further, the proposed model is simulated with different top electrode metals and dielectric materials to demonstrate the formation of optimal stack for the desired application. Then, the proposed selector model (1S) is integrated with RRAM model (1R) and the compatibility of the devices is verified. Moreover, from the presented 1S-1R model, various parameters for the establishment of CBA such as read/write voltages for selected/unselected trails are predicted and substantial conditions for sneak path current reduction such as non-linearity, Roff/Ron ratio and off-current (10 nA) are also evaluated.

This study presents a self-sustainable soil energy harvesting system with a rapid startup circuit. The proposed system enables the operation from input voltage as low as 0.3 V, and to up-convert the output to 3.3 V. The system is capable of extracting maximum power from the soil energy source. An efficient startup circuit that performs low initial charging time for a supercapacitor is presented. Experimental results show that the proposed system has a peak end-to-end efficiency of 58.48%. Also, the initial charging time of the supercapacitor is lowered by 2.54× as compared to the design without the startup circuit. The proposed system has been verified with off-the-shelf components.

In this study, a new tier partitioning algorithm for three-dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through-silicon vias (TSVs) subject to fixed-outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover and complement mutation, is employed for optimisation of design variables. Experimental results exhibit that the authors proposed method reduces the average number of TSVs by 45.75 and 44.68%, as compared to taboo search and simulated annealing-based 3D partitioning methods. It also reduces the average number of TSVs, maximum power density among the layers and average layer area by 28.34, 40.29, and 27.85%, respectively, as compared to thermal-aware 3D partitioning technique. The results of their proposed algorithm demonstrate the efficiency and effectiveness in tier partitioning for 3D ICs over existing methods.

This study describes a field-programmable gate arrays (FPGAs) based technique, which aims to significantly improve the resolution of complementary drivers in full-bridge DC–DC converters. An algorithm for precise adjustment of both the duty cycle and the frequency of the pulse width modulator (PWM) is presented. It is experimentally verified by software simulation and FPGA hardware implementation. The results prove that the designed 12-bit digital PWM is able to provide switching frequency of 100 kHz in the range of 99.61 [99.51–99.70] kHz [mean value (95% confidence interval)] using clock frequency of just 160 MHz. In comparison, the conventional counter-based PWM gives the same output resolution at operating frequency of 410 MHz. In addition, the proposed algorithm is scalable and could be used to provide better resolution even at higher clock frequencies >400 MHz. For example, if phase-locked loop is 480 MHz then the conventional counter for 100 kHz PWM has a resolution slightly >12 bits, while the proposed algorithm could extend the resolution up to 14 bits. Due to the high reliability of the FPGA technology, the proposed PWM control is applicable in highly critical medical systems, such as electrosurgical devices.