Interval observer design and related techniques have been researched and applied in many engineering fields and continue to be an active research area in the estimation and control society for the last two decades. An Interval observer is a special class of observers that generates a bounded interval vector for the real state vector in a guaranteed way under the assumption that the uncertainties are unknown but bounded. Some of the basic concepts and the main developments in the designs and applications of interval observer for continuous-time, discrete-time (linear and non-linear), fuzzy and switched systems are reviewed in this work. It also provides a brief discussion of the main approaches in this area with clear descriptions of their structures and future directions.

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm². For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.

This study presents a novel implementation technique for linear phase variable bandwidth finite impulse response (FIR) filters with a noticeable reduction in transition bandwidth as well as hardware complexity. In this proposition, concept of Farrow structure based design technique is effectively utilised; whereas the fixed sub-filters are constructed from a generalised interpolated bandpass method based low-pass FIR filter by means of different techniques such as interpolation, up-sampling and masking. Simulation results have shown the frequency response characteristics of several variable bandwidth FIR filters, designed with the help of the proposed architecture. Simulation results have shown a drastic reduction of transition bandwidth resulting from the proposed variable bandwidth FIR filters of up to ∼70–80%, when compared with other state-of-the-art filtering techniques, with a significant reduction in hardware complexity of up to ∼50%.

This study introduces a new approach for realising a sinusoidal oscillator with three outputs, using an active-resistor-capacitor (RC) approach. Using the proposed approach, a new circuit employing three current feedback operational amplifiers and passive components is further introduced. The circuit employs two grounded capacitors and four resistors, out of which one is grounded. The new circuit based on the proposed generalised approach is relatively insensitive to the parasitic effects of active elements, and easy to design, by way of non-interaction of frequency and condition of oscillations. The proposed approach and the new proposed circuit provide three outputs, two of which are at low impedance nodes. The proposed generalised approach and the new circuit are verified through simulation and experimental results, using commercially available AD-844s integrated circuits and passive components. Thus, the work advances the existing knowledge on the active-RC oscillator design.

Simple and efficient frequency compensation technique for a four-stage amplifier is presented in this study. Using a differential feedback stage and a single Miller capacitor on its output, the frequency compensation network is formed. The proposed configuration is described via matrix description. Meanwhile, an analytical transfer function is calculated. The proposed amplifier demonstrates low die occupation because of the small value of the compensation capacitor while shows acceptable frequency response regarding gain bandwidth and phase margin values. In addition, the design procedure is simple compared to the previous state-of-the-art. The HSPICE circuit simulator and TSMC 0.18 µm CMOS technology were exploited to verify theoretical presentation.

Emerging devices such as double gate carbon nanotube field effect transistors (DG CNTFETs) have opened up manifold possibilities for reconfigurable logic design. The thickness of gate oxide and the employment of inhomogeneous dielectrics over and under the carbon nanotubes (CNTs) impact the operation of DG CNTFETs. In this work, the dielectric constant and the thickness of the gate oxide are optimised to suppress the ambipolar conduction in CNTFETs. A multi-objective genetic algorithm-based approach is proposed to optimise these parameters. The contributions in this study are two-fold: firstly, a DG CNTFET is fabricated with the optimised parameters. By exploiting the ability to select the conduction behaviour using a second gate in the fabricated DG CNTFETs, the device is electrostatically programmed to behave as an n or p-type CNTFET. Secondly, a one instruction set computer is simulated with the optimised model of DG CNTFET. A universal static logic cell which implements 16 logic functions, a D-Latch and a D-FF were built with DG CNTFETs. The logic circuits with polarity-tunable DG CNTFETs outperform other logic structures. There is a 40% betterment in performance primarily due to the reduced number of logic levels and by 25% due to the reduced delay.

The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall energy efficiency of the link. Also, compared to existing passive terminated interconnect with current-mode receivers at all the points, the proposed link deploys low impedance current-mode receivers providing active terminations at both the ends of the interconnect and high-impedance voltage-mode receivers, which do not consume any portion of the signalling current, at the intermediate nodes of the interconnect which further lowers the required transmitter signalling current. A mixed-mode or hybrid transceiver architecture has been proposed for the aforementioned link, which can act either as a current-mode transmitter or a current-mode receiver or a voltage-mode receiver. The architecture has been implemented in 0.18-μm complementary metal oxide semiconductor technology for an interconnect of length 4 mm and having five transceiver nodes. The total energy efficiency of the architecture is 0.70 pJ/b for a speed of 3.0 Gb/s.

In wireline communication systems, InterSymbol Interference (ISI) may also occur by termination mismatch at either end of a long channel. Termination resistors, characteristic channel impedance, and connectors may get altered by temperature and supply voltage variations during operation. Wireline front-ends may exercise on-the-fly termination calibration to mitigate ISI during operation. Here the authors demonstrate the impact on signal integrity of an on-the-fly termination calibration using moderated coarse calibration steps. They introduce a resistance termination calibration scheme that enables fine steps and considers high-current density effects during ElectroStatic Discharge events. The simulation results of an implemented calibration scheme within a front-end operating at 3.2 Gb/s ensure open data eyes during on-the-fly termination calibration. A comparison with a conventional scheme illustrates how coarse calibration generates undesired reflected waves, handicapping signal integrity.

Three simulated floating inductor (SFI) circuits containing a single DDCC− called as minus-type differential difference current conveyor are proposed. These SFIs are series lossy, parallel lossy and negative lossless ones. The used DDCC− in each of the proposed SFIs has a single Z terminal. Without needing any passive element matching constraints, each of the proposed SFIs is composed of a minimum number of passive elements. As application examples, second-order current-mode (CM) and voltage-mode low-pass (LP) filters derived from the proposed series lossy SFI are given. Also, a fourth-order CM Butterworth LP filter example is presented as another application. A second-order CM high-pass (HP) filter and an RLC resonant circuit obtained from the proposed parallel lossy SFI are given. All the simulations are achieved via SPICE program. Moreover, some experimental results for the proposed lossy SFIs and CM HP filter are given in order to show the performances.

This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters shifts (gain, P _out, drain efficiency: DE, and P _sat), the reliability of different tests have been compared. To explain and confirm these effects according to the degradation data, the dominant physical phonemes involved have been studied and the failure modes of the metal-oxide-semiconductor field-effect transistors have been examined and proved with the SILVACO-ATLAS simulator. What supports finding a relationship between the shifts of RF electrical parameters to failure physical phenomena caused by impact ionisation. The behaviour degradation of N-LDMOS is related to interface states generated by hot carriers (traps) and by the electrons that are trapped, which leads to an accumulation of negative charge at the Si/SiO₂ interface. At low temperature, the interface states are created more, due to a maximum impact ionisation rate targeted in the gate edge area. Finally, RF behaviour reliability analysis has been discussed.

Memristor-based stateful logic circuits can perform logic operations and logic value storage, which creates an intriguing opportunity for the implementation of an advanced computational architecture. This study proposes a novel memristor-based stateful logic implementation. Specifically, the presented approach is capable of realising two-input or multi-input AND, OR, NAND and NOR operations, and single-input COPY and NOT operations. In each logic gate, non-volatile resistances of memristor are used as input and output states, thus enabling stateful logic operations. Compared with several existing approaches, the proposed method can lead to a multi-functional stateful logic circuit, performing multiple stateful logic operations simultaneously. The effectiveness of the proposed design is demonstrated with the simulation results of MATLAB and SPICE.

Due to feedback amplifier analysis simplification, Miller theorem, feedback theorem and Gray–Searle theorem are the most used tools on the calculation of the frequency response. However, they are only approximated results and then are invalid for overall closed-loop voltage gain of the frequency response. The traditional feedback theory, Miller theorem and Gray–Searle theorem are troublesome due to the significant difficulty of using the Kirchhoff's voltage/current law and Thevenin equivalent theorem. Especially, the utilisations of the Kirchhoff's voltage/current law and Thevenin equivalent theorem will be impractical for the complicated differential amplifier with the active load that contains four dependent sources and three bridge elements. The study proposes exact and algebraic frequency response analysis of a feedback amplifier by using the authors series research-Chen's Electric Unifying Approach with L'Hospital rule and Cramer's rule to take the place of those traditional approaches. Some experimental and mathematical results have exploited the fact that the proposed approach can yield the more effective and practical DC quiescent analysis with bias values and AC frequency response analysis with two junction charge-storage capacitances for the common-emitter amplifier with emitter resistance. Some experiments are provided to demonstrate the effectiveness of the proposed method.

Voltage sag and short interruption lead to the tripping of sensitive equipment and cause the economic loss of the industry users. A programmable logic controller (PLC) is essential equipment used in the industrial process. However, there is no detailed understanding of the sensitivity of PLC under voltage sag and short interruption. The response characteristic of PLC under voltage sag is studied. This study proposes a new testing method, called the dichotomy test method (DTM) to do the test. This study builds the testing platform and tests the sensitivity of six PLCs from five famous PLC manufacturers. The testing considers the characteristics of voltage sag, including magnitude, duration, point-on-wave, phase-angle-jump, different supply voltage, slow recovery voltage sag, multiple voltage sags and so on. The tests prove that DTM has the advantage of accuracy, robustness and workload, compared with the traditional test method. The quantitative and qualitative response characteristics of PLC under voltage sag are obtained.

This study proposes an input interface based on a magnetic tunnel junction (MTJ) to initialise the magnetisation directions of all-spin logic (ASL) circuits. It is convenient to input logic 0 and logic 1 to ASL circuits by changing the current direction into the MTJ. The impacts of current density, tunnel magneto-resistance (TMR), and resistance–area product (RA) on the input interface are studied. The results indicate that smaller TMR and RA of the materials are helpful in reducing the energy dissipation of the input interface without increasing the delay time, and the current density has a large range of options. Moreover, two kinds of output structures, single-input multi fan-out (SIMF) and multi-input single fan-out (MISF), are proposed to provide signals for subsequent ASL circuits. It is found that the SIMF structure is suitable for the condition of fewer output terminals, but the MISF structure is especially useful for large-scale ASL circuits that contain many identical input ports. The above-mentioned conclusions can provide guidelines for optimising the device materials and output structures of ASL circuits.

This study presents a compact wide stopband microstrip diplexer which is designed based on a novel resonator structure. This novel resonator consists of a main hairpin cell loaded by a smaller hairpin and T-shaped cells. The presented diplexer operates at 3.46 and 4.75 GHz for IEEE 802.16 worldwide interoperability for microwave access (WiMAX) and IEEE802.11a Wireless LAN applications, respectively. The main advantages of the proposed diplexer are its flat channels, two wide bandwidths, attenuated harmonics, low insertion losses better than 0.18 dB, several transmission zeros and sharp frequency response. From first up to fifth harmonics of the proposed diplexer are well attenuated with the maximum harmonic level −20 dB. Meanwhile, the simulation results show that the presented design can suppress harmonics up to 44 GHz. In other words, the harmonics from the 1st up to 12th are suppressed. The group delay at both channels is lower than 1.1 ns, which is good for a microstrip diplexer. This good performance is obtained, while the overall area of the designed diplexer is only 0.037. Based on the comparison results, the proposed diplexer has a compact size, the minimum group delay and a wide stopband rejection. The proposed diplexer is fabricated and measured. Both simulation and measurement results are in good agreement.

In this study, an improved capacitor-less flipped voltage follower (FVF) low drop-out regulator (LDO) with active feed-forward compensation (AFFC) and an efficient slew-rate enhancer (SRE) circuit is presented. In capacitor-less FVF LDOs, the dominant pole is placed at the gate of the power metal oxide semiconductor field effect transistor (MOSFET) which demands minimum load current for the feedback-loop to be stable. The proposed compensator has miller compensation along with AFFC which helps to eliminate the minimum load demand for the feedback-loop of the LDO to be stable by shifting the right half-plane (RHP) zero of power MOSFET to left half-plane (LHP) zero. This LHP zero proportionally varies with the first non-dominant pole at the output of the LDO as the load current varies from light load to heavy load and extends the unity gain frequency of the proposed LDO. The SRE circuit supports fast load transients with edge time of 50 ns and achieves less voltage spike without consuming any power at steady-state. This LDO is implemented in technology with a drop-out voltage of 200 mV and can drive the load current range of 0–50 mA with regulated output voltages from 1.2 to 1.6 V. It settles faster with the settling time of 250 ns and has the quiescent current of .

This study presents a robust design of a trigger pulse generator that produces trigger pulses of variable widths/durations that are tuned using an external control as per the requirements. The proposed design comprises two elementary modules: a delay element and an XOR circuit. The proposed circuit is implemented using a 16 nm CMOS technology node and simulation results have been verified using the SPICE simulator. Various performance parameters such as power consumption, power delay-product, energy-delay product and impact of key circuit parameters [supply voltage (V _DD), channel length (Lg), gate width (Wg), channel doping concentration (N _A), oxide thickness (T _OX), threshold voltage (V _T) and carrier mobility (µ _o)] on the duration of trigger pulses have been studied in-depth and performance parameters are compared with circuits already available in the literature. The proposed circuit produces trigger pulses of a minimum width of 191.3 ps at a nominal supply of 1.0 V with an average power consumption of 160 nW. The width of the trigger pulses can be varied from 191.3 to 457.2 ps using an external control from 1.0 to 0.7 V, respectively, at 16 nm technology node.

In this study the authors propose a novel and straightforward design procedure for the single-ended ring oscillator (SERO). This procedure determines the values of the circuit parameters to reach the desired oscillation frequency while the power consumption and the area are minimised and the noise is kept below the desired value. Furthermore, the authors analyse the SERO and suggest a practical formula for the oscillation frequency. In comparison to the conventional equations, the derived formula is accurate as well as explicit. The accuracy of the proposed frequency equation is verified using simulation. The average of the absolute errors over a wide range of parameters is 2.52%, and the worst case error is 9.64%. In addition, the power consumption of the SERO is analysed and a formula is presented for estimating the power consumption.

This study presents a novel voltage-programmed, amorphous-indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT)-based active-matrix organic light-emitting diode (AMOLED) pixel circuit. The circuit utilises the threshold voltage (V _TH) sensing ability of a diode-connected transistor to compensate for the spatial as well as the temporal variation of the threshold voltage of the driving transistor and supply a constant current to the OLED. The circuit has been simulated in Cadence Spectre using a-IGZO TFT and OLED simulation program with integrated circuit emphasis (SPICE) models, and the analysis is presented to prove the V _TH compensating capability of the proposed circuit. For small currents, about 50 nA, the error is suppressed to <9% whereas for large currents, about 2.5 µA, the error is only 1.05%. This performance has been achieved using only five TFTs and two storage capacitors.

This paper presents a single loop 3^rd order discrete-time Sigma–Delta Modulator () using a single operational amplifier (Op-Amp). The proposed utilises delay-based discrete-time integrators and a single Op-Amp is used to implement all the integrators of the proposed design. The delay-based design helps in relaxing the settling time requirement of an integrator, also the error due to slewing in the output of the integrator is avoided. A switched capacitor Op-Amp based proposed design is simulated in standard 180~nm CMOS technology with a resolution of 10.75 bits. The proposed achieves a signal-to-noise-distortion ratio (SNDR) of 66.48 dB and dynamic range (DR) of 70 dB. An input signal of −4 dBFS magnitude at a frequency of 2.125 kHz is sampled with a sampling frequency of 1.024 MHz. The proposed circuit is designed for a bandwidth (BW) of 20 kHz with an over-sampling-ratio (OSR) of 25.6. The proposed modulator achieves a figure-of-merit (FOMS/FOMW) of 156.48 dB/0.290 (pJ/conversion-step) with the total power consumption of 20 µW at 1.8 V supply voltage (VDD). A Monte-Carlo simulation for the SNDR of the proposed design is done and the achieved mean and standard deviation (SD) is 66.09 dB and 1.025 respectively for 1000 samples.

A dual-frequency band low input power rectenna is proposed in this study. The rectenna is comprised of a co-planar waveguide (CPW) rectifier integrated with a rectangular split ring antenna loaded by a spiral strip line. A single diode series connection topology is used to miniaturise the losses at low input power. A spiral coil in addition to two short circuit stubs are used as a matching network for maximum power transfer between the antenna and the rectifying circuit. The proposed rectenna operates at low input power with relatively high measured RF-DC conversion efficiency up to at input power of at the first resonant frequency and at at the second operating frequency with a resistive load of . The measured rectenna sensitivity (the rectenna ability to receive low power with acceptable conversion efficiency) reaches up to with a conversion efficiency of and at and , respectively, and a DC output voltage of . The measured efficiency is over from to and from to at and , respectively.

This study proposes a new scheme for rail-to-rail input StrongARM latch comparator. Additional differential input p-type metal-oxide-semiconductor (PMOS) and cross-coupled n-type metal-oxide-semiconductor (NMOS) transistors have been introduced to achieve the rail-to-rail input range. The proposed scheme offers low-energy consumption of 15.2 fJ and a high speed of 3 GHz, which makes it attractive for energy harvested Internet of Thing applications. The proposed architecture is fabricated in 65 nm complementary metal-oxide-semiconductor (CMOS) technology and the functionality is verified using post-layout simulations and chip measurements.

A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP filter gain is unity for the current output while it is adjustable for the voltage output via a grounded resistor. However, a single passive component matching condition is needed for the proposed MM AP filter. Complete non-ideal analysis by taking into account all the parasitic resistors and non-ideal gains of the VCII+ is performed. The presented theory is verified through SPICE simulations by using supply voltage of ± 0.9 V and 0.18 μm Taiwan Semiconductor Manufacturing Company complementary metal oxide semiconductor technology parameters.

In this study, we compared the timing and its random dopant fluctuation (RDF)-induced variations in nanometre conventional and negative-capacitance CMOS (NC-CMOS) inverters. The authors found that the transition delay in the NC-CMOS inverter exhibits a strongly dependence on the viscosity coefficient (ρ) of the ferroelectric (FE). Only NC-CMOS using sufficiently low ρ with smaller response time to baseline CMOS can be considered as a low-power device with a smaller propagation delay. Due to the steeper transient subthreshold swing and lower threshold voltage (V _th), the timing parameters, e.g. rise time, fall time, high-to-low transition, low-to-high transition, and propagation delay were all reduced. Furthermore, RDF-induced timing variations can be effectively suppressed by the negative capacitance effect provided by the FE capacitor and the fluctuation of static DC power also drops, and this immunity to RDF-induced timing variations increases with increasing FE thickness (T _FE). Our analysis was verified by technology-aided design simulation and can provide useful insights into future studies of low-power CMOS digital circuits.

This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron velocity, threshold voltage (V _th), electron mobility, and sub-threshold swing (SS) of these devices has been performed. Results reveal a 43.85% improvement in SS and 9.83% decrement in V _th for GaN-BTG-MOSFET. Furthermore, the frequency analysis has been performed in terms of scattering (S) parameters, cut-off frequency (f _T) and maximum oscillator frequency (f _MAX) to show how the device is also suitable for radio frequency applications. Furthermore, the study of parametric variation of GaN-BTG-MOSFET with the change in channel length, oxide thickness (t _ox), and doping concentration has also been presented. Results show that GaN-BTG-MOSFET can act as a promising structure for further scaling down of the trenched MOSFET and assures better performance for sub-20 nm trenched MOSFET.