Physical unclonable function (PUF) is hardware-specific security primitive for providing cryptographic functionalities that are applicable for secure communication among the embedded devices. The physical structure of PUF is considered to be easy to manufacture but hard or impossible to replicate due to variations in its manufacturing process. However, a large community of analytics believes hardware-based PUF has paved the way for its realisation in providing dependable security. In this study, the authors have thoroughly explored the architecture, applications, requirements, and challenges of PUF that provide security solutions. For presenting the literature, they have designed a taxonomy where PUFs are divided under two main categories, including non-silicon and silicon-based PUF. Currently, there is no comprehensive survey that highlights the comparison and usability of memory-based and analogue/mixed-signal based PUF that are considered to be suitable as compared to counterparts. In a similar vein, they have presented the network-specific application scenarios in wireless sensor network, wireless body area network and Internet of Things and then identified the strong, weak and controlled PUF in a categorical manner. Moreover, they have presented a number of prospective limitations that are identified in PUF structures and then identified the open research challenges to meet the desired security levels.

In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors. This method has reduced the power consumption greatly. Additionally, by employing reversible logic in the 2:1 multiplier, the power consumption and the number of stages were dropped and obtaining a faster converter was considered as the other breakthrough. The simulation was carried out in 1.8 V supply voltage and power consumption of 330 µW while the sampling rate was equal to 2GSample/s.

The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V – 28 µA reference circuit, and a 7.50 µA/V operational-transconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance cut-off frequency , gain bandwidth product and maximum oscillating frequency . Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated logic cells used for implementing parallel prefix tree structure. The FM validates the final comparison based on results obtained from the CEM. The presence of regular very large-scale integration topology in the proposed structure allows the analytical derivation of the area in terms of total number of transistors present in the design and total delay encountered in input–output flow as the function of input operand bitwidth. Spectre simulation results have been presented using 0.18 µm complementary metal–oxide–semiconductor (CMOS) technology at 1 GHz. The main advantages of the proposed comparator are minimum input–output delay of 0.57 ns, minimum fan-out-of-4 delay of 9.5 ns and low-power dissipation of 1.03 mw as compared with existing comparators designed using 180 nm CMOS technology for 64 bit comparison.

A high-precision measurement method, based on multiple sampling, is proposed for the time interval of two signals in this study. A time interval measurement circuit integrated into the time-to-digital converter (TDC), is designed based on this high-precision measurement method. In the TDC, the authors use two identical delay lines as the holding module to ensure the two signals with a constant time interval. The TDC samples the two signals multiple times by a clock signal, whose period is shorter than that of the delay line. Consequently, the problem of limited resolution caused by a mismatch between delay lines in the delay-line structure can be avoided, and the precision of the output can be improved. The proposed TDC is designed and simulated in Semiconductor Manufacturing International Corporation (SMIC) 0.18 μm complementary metal–oxide–semiconductor process. Simulation results show that the differential non-linearity and the integral non-linearity are always less than one least significant bits. The proposed TDC achieves input dynamic range of 0–32.13 ns and time resolution of 9 ps.

In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.

The lower photo-generated current in a top cell limits the performance of the tandem solar cell by restricting the short circuit current density. To overcome this, the top cell must be suitably designed which can utilise the excess photo-generated current of the bottom cell. In this proposed work, an InGaP/GaSb tandem cell is designed by incorporating one-dimensional (1D) GaAs quantum superlattice in the top InGaP cell. The model is simulated using the ATLAS device simulator. The performance of the cell is assessed in terms of short circuit current density (J _sc), open circuit voltage (V _oc), fill factor and efficiency (E _ff). A detailed analysis of the top cell is carried out to validate the proposed model. The designed tandem cell shows a significant improvement in terms of J _sc (2075.88 mA/cm²) and E _ff (46.58%).

The versatility of the use of zinc oxide in numerous applications has attracted the attention of various academic research workers and industries. Various micro and nanostructures of zinc oxide have been explored owing to different growth methods and applications. In this research work, zinc oxide nanoflower is grown on a glass substrate using un-complicated and a low-cost hydrothermal method. Hydrolysis of zinc nitrate is done in a basic medium. The main criteria followed for such a structural growth is the control of the pH of the solution precursor. The grown structure is further characterised by using the scanning electron microscopy, energy dispersive spectroscopy and X-ray diffraction. Synthesised zinc oxide nanostructure is utilised as a piezoelectric material in a nanogenerator. The maximum power per unit area of 2.6 mW/m² is achieved. Simulation results of the similar zinc oxide nanostructure is also presented, which substantiate the experimental results.

Independent component analysis (ICA) is an unsupervised learning approach for computing the independent components (ICs) from the multivariate signals or data matrix. The ICs are evaluated based on the multiplication of the weight matrix with the multivariate data matrix. This study proposes a novel Pt/Cu:ZnO/Nb:STO memristor crossbar array for the implementation of both ACY ICA and Fast ICA for blind source separation. The data input was applied in the form of pulse width modulated voltages to the crossbar array and the weight of the implemented neural network is stored in the memristor. The output charges from the memristor columns are used to calculate the weight update, which is executed through the voltages kept higher than the memristor Set/Reset voltages (±1.30 V). In order to demonstrate its potential application, the proposed memristor crossbar arrays based fast ICA architecture is employed for image source separation problem. The experimental results demonstrate that the proposed approach is very effective to separate image sources, and also the contrast of the images are improved with an improvement factor in terms of percentage of structural similarity as 67.27% when compared with the software-based implementation of conventional ACY ICA and Fast ICA algorithms.

The study presents two new realisations of bipolar two-quadrant implicit RMS-to-DC converter and four-quadrant multiplier/divider employing two VDTAs (voltage differential transconductance amplifier) and grounded passive elements. The converters provide the operating frequency of up to 10 MHz with increased precision in the processing of input currents signals, when compared to known realisations. Errors related to the signal processing and errors bound were investigated and presented in this study. The results obtained from the simulation tests in HSPICE and the experimentally realised models of the converters showed a good match with the theoretical anticipation. The maximum power consumption of the converters is 2.82 mW, at ±1.2 V supply voltages.

The crossbar array implementing the weighted sum computation and weight update operation is a promising hardware accelerator for neuromorphic computing. However, the voltage drop caused by the current flowing through the access lines could be aggressive for the resistive crossbar array in a fully parallel fashion. In this study, the authors analysed the impact of the line resistance on the crossbar array based on the SPICE simulation. It implies that the scale of the crossbar array and the ratio of line resistance to resistive random access memory resistance bring great influence on the performance of the crossbar array. Also an scheme of optimisation has been proposed to diminish its influence. Furthermore, considering line resistance, multi-layer perceptron based on crossbar array has been simulated with SPICE on Modified National Institute of Standards and Technology dataset. Those results could provide design guidelines for the practical hardware implementation of the neuromorphic accelerator.

A fixed-width multiplier receives two n-bit operands and generates an approximate n-bit product as the output. It truncates part of the partial products and employs an appropriate error compensation circuit in order to reduce the approximation error. In this study, a new error compensation circuit for the fixed-width multiplier has been proposed which utilises the correction vector (CV) and modified minor CV. The proposed error compensation circuit is capable of minimising both the mean error and the mean-square error. Post-synthesis results for 16-bit of fixed-width multiplier demonstrate that the proposed circuit has 3.50, 39.24, 42.91 and 44.91% reduced delay, area, power consumption and power–delay product when compared with the existing design reported in the literature.

A novel high-frequency lossy uniform transmission line model is presented in this study. Novel features include a compactness of form and a level of simplicity that confers enhanced simulation efficiency in practical applications. Although specifically developed to target implementation in generic versions of SPICE, the compact high-frequency model can be implemented using only four lines of netlist syntax in the case of circuit simulators that offer native Laplace equation support. Featuring a broadband frequency response characteristic that is defined by only four parameters, the compact HF model is based on a novel theoretical approach that elegantly connects the four model parameters to physical line parameters using only elementary line characterisation data. Important and perhaps surprising differences between the new model theory and classical textbook theory are highlighted and discussed. The lessons learned are then incorporated into a second hybrid model featuring a higher level of complexity that combines both new and classical theoretical approaches into a single set of model equations that are better suited for atypically small controlled impedance structures such as silicon interposers and on-chip clock and data distribution schemes.

An impulse radio ultra-wideband (IR-UWB) transmitter (TX) consuming ultra-low power is presented. The low-complexity topology features control of the power spectral density (PSD) and central frequency for a broad range of applications. The PSD and frequency adjustment are accomplished by employing a tunable pulse generator and an adjustable driver. The IR-UWB TX suitable for on–off keying coding is fabricated in a low-cost 180 nm UMC CMOS technology and occupies the total die area of 0.63 mm². The measurement results show the transmitter output swing of 320 mVpp (peak-to-peak amplitude) with the pulse duration of 0.6 ns, and the spectrum covering the frequency range from 3 to 7.5 GHz. The total DC power consumption is 1 mW resulting in energy consumption of 5 pJ/pulse at 200 MHz data rate.

Multivalued logic (MVL) is an effective way to increase device integration in semiconductor circuits. The major problem for MVL implementation is the availability of proper semiconductor devices. Different quantum structures and their application in different semiconductor devices help them implement the MVL circuit. In this work, the designed graphic user interface will provide more flexibility to the user to highlight the application of different semiconductor devices for MVL implementation. Users can experience the variation of device's characteristics and their feasibility in the application of MVL effectively with this software package.

An adaptive multi-resolution simulation (AMRS) framework for fast and accurate simulation of high-fidelity models of power electronic circuits (PECs) is presented in this study. The wide span of eigenvalues makes PEC simulation prohibitively slow. This problem can be tackled using the proposed approach. Singular perturbation approximation is used to extract simplified models by ignoring the transient contribution of the non-dominant eigenvalues. Simplified models of different orders or resolutions, each corresponding to a particular level of accuracy are derived on the fly at no additional computational cost. The simulation engine is set such that it adaptively switches across resolutions based on a predefined tolerance during the simulation. This approach is advantageous in the sense that instead of simulating the original model over the entire time-range, a combination of the original and simplified models is simulated. The combined use of the original and the simplified models is thus shown to be a powerful tool for efficient and accurate simulation of PECs. The examples illustrated, show that the AMRS approach makes the simulation considerably faster and ensures the complete response of the system is obtained with negligible error. The method is illustrated on a Class-E amplifier and a DC–DC buck–boost converter.

Portable automatic seizure detection systems can greatly improve the quality of life of epileptic patients. To improve the performance of seizure detection, independent component analysis (ICA) is implemented in these systems to extract artefacts of electroencephalogram (EEG), and then wavelet denoising method is used to remove the artefacts. However, classical ICA requires post-identification of the components containing artefacts, which cause inefficiency. In this study, integrated circuit implementation of fast ICA with reference algorithm and wavelet denoising method is carried out to enable on-chip artefact extraction and removal without post-identification. This system consists of extraction and removal module, which are designed highly parallel to speed up computation, and therefore, save time for seizure detection. The presented system is verified on Kintex-7 field-programmable gate array using synthesised signal and real EEG data. Experiment results show that the designed system is fully functional and speeds up the artefact removal process.

This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

An in-depth circuital analysis of an energy-efficient high peak power impulse radio ultra-wideband (IR-UWB) pulse generator monolithic microwave integrated circuit (MMIC) design is presented. The proposed IR-UWB pulse generation process is explained in detail. A trade-off between the peak output power level and the frequency of operation is discussed. The proposed circuit is optimised for the highest possible peak output power in the 3–5 GHz UWB band for ranging and radar application. The presented IR-UWB pulse former makes use of the cascode heterojunction bipolar transistor (HBT) configuration for signal scaling operation instead of the common emitter configuration. The proposed cascode pair configuration results in higher output voltage swing as well as reduced power consumption. The effect of coupling capacitors on amplification factor of the pulse former stages as well as impedance profile of the distributed transmission line is discussed in great detail. The temperature-dependent parasitic component in the proposed circuit is studied. Its effect on the transient behaviour of the proposed IR-UWB pulse generator is analysed, which is important for IR-UWB beamforming applications. The required mathematical model for the parasitic effect is derived and explained.