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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 14, Issue 3, May 2020


Volume 14, Issue 3

May 2020

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    • Design and development of symmetrical super-lift DC–AC converter using firefly algorithm for solar-photovoltaic applications
      Reduction of Drain Induced Barrier Lowering in DM-HD-NA GAAFET for RF Applications
      Design and optimisation of a novel structure capacitive RF MEMS switch to integrate with an antenna to improve its performance parameters
      Suppression of ambipolarity in tunnel-FETs using gate oxide as parameter: analysis and investigation
      Accelerating low-voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques
      65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing
      Dual band stop filter design via frequency transformation and synthesis with lumped resonators
      8-bit serialised architecture of SEED block cipher for constrained devices
      11 Gb/s 140 GHz OOK modulator with 24.6 dB isolation utilising cascaded switch and amplifier-based stages in 65 nm bulk CMOS
      Adaptive analogue calibration technique to compensate electrode motion artefacts in biopotential recording
      Design approach to improve the performance of JAMFETs
      6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process
      Supervised learning for early and accurate battery terminal voltage collapse detection
      High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4:2 compressor design in CNFET technology
      Flexible structures of lightweight block ciphers PRESENT, SIMON and LED
      Parallel architecture of power-of-two multipliers for FPGAs
      Exploiting uncertain timing information in time-based SAR ADCs
      Relay-based identification of Wiener model

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