This study presents an extendable full-colour light emitting diode (LED) display based on field-programmable gate array implementation. The LED display panel system includes memory management, image format conversion, serial parallel interface (SPI) interface, local scan techniques, LED driver and pulse width modulation (PWM) data control. To reduce I/O ports, data transmission system uses SPI interface to send the PWM data to the LED panels. A novel local scan technique, which could use a lower frequency for data transmission and achieve higher frame rate for LED display, is proposed. Each display module contains local memories for data self-scanning to LED. The display continues even if there is no new data input. The advantages are that the display rate does not care about the speed of data transmission. Only motion area, rather than complete frame, required sending data to display, which can greatly improve data bandwidth. This is very useful for high-resolution display system since even low data rate can achieve the fast display refresh. This approach is a module-based design, which can easily be extended to any size with auto re-configuration without using embedded processor.

In the presence of deep submicron noise, providing reliable and energy-efficient network on-chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)-based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi-bit error protection while achieving high-energy savings. This is achieved by calculating two-dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high-energy savings are achieved. The results show that the proposed scheme reduces the energy consumption up to 51.7% as compared with other schemes while achieving the target link reliability level. Also, it shows improved network performance as compared with ARQ-based scheme and close to forward error correction-based schemes.

The purpose of this research is to find out a perpendicular nanomagnetic cell with optimum dimensions by using Object Oriented Micromagnetic Framework (OOMMF) simulation. The optimum perpendicular nanomagnetic cell is characterised and the effect of nano-size on the performance of the cell is explored. Nanomagnetic basic gates are implemented by applying the proper arrangement of nanomagnetic cells. The optimum size of nano cell is 50 × 30 × 5 nm. In this survey, all designs are implemented by employing 3-input and 5-input minority gates. The clock signal, which is a uniform magnetic external field, is needed for proper performance of gates. An irreversible 2-input XOR gate is suggested by these gates based on perpendicular nanomagnetic cells. Moreover, the power dissipation is a major concern in digital circuits. It was proved that the heat dissipation will be very low in reversible circuits. Therefore, the reversible XOR gates are suggested by applying the proposed gates in this study. The correctness of operation of the presented gates is verified by using MagCAD tool. According to the simulation results, the proposed 2-input XOR gates in a single layer have significant improvement in terms of gate count, delay and complexity in comparison to the previous design.

An all-digital first-order single-bit time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the per-stage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the per-stage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

Memristor, a passive circuit element got tremendous research attention for its in-memory computation. In this study, it was identified that controllable resistive state transitions exist within a single memristor. On the basis of this realisation, a simple but unconventional implementation of memristive up and down counters was presented. Furthermore, a dual up–down counter was developed, which can mimic any real-time process variations. To demonstrate its practical application, a counter-based memristive automatic irrigation system was explicated, which provided optimised utilisation of electrical and water resources. The proposed study opens up a new purview in the area of future non-Von Neumann computer architectures and its potential electronic applications.

This study presents the control mechanism of a DC–DC buck converter using generalised predictive control by approximating the plant model to a stable first-order plus dead time (FOPDT) model. As most of the higher order plant dynamics can be represented by an FOPDT model, this study is limited only to a stable FOPDT dynamics system. In this work, a relation between FOPDT model parameters and weights of the cost function is derived. The controller design procedure is then verified by implementing voltage mode control of the DC–DC buck converter in the case of inactive constraints. Jury's stability criteria are used to analyse the stability of the closed-loop system. The implemented algorithm is then verified using simulation in MATLAB/Simulink, as well as the hardware implementation of the pre-computed control algorithm.

Multi-level inverter gives low total harmonic distortion when compared to the two-level inverter. A huge number of switches are required to enhance the performance of multi-level inverters. Conventional neutral point clamped (NPC) three-level inverter needs 12 switches to control a single three-phase load. In this research, dual input and output reduced switch count three-level inverter topology with a minimum number of switches is proposed to reduce the system cost, weight and driver circuits. The sinusoidal pulse width modulation (SPWM) control techniques are developed to control NPC dual inverters. The dual inverter with constant frequency and variable frequency mode are simulated by MATLAB Simulink software and the results are discussed in detail. The analysis plan with 15 different combinations of input parameters is developed as per the Box–Behnken method and the results are compared and discussed. Also, the results such as output voltage, V _THD , I _THD and efficiency are analysed by regression analysis and the derived regression equations can be used to predict the output parameters. The combination of input parameters and dual inverter topology, which give optimum output values are identified by composite desirability analysis. This dual inverter reduced switch count topology can be used for renewable energy applications to reduce the inverter cost and space.

In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

Physical design is a crucial stage determining the ultimate performance of very-large-scale integration design in which the constraint application plays an important role. Unfortunately, the resulting influence and propagation of the constraint is unknown so far and needs to be studied comprehensively. Here, the authors attempt to evaluate the propagation of the constraint in two different optimisation styles, i.e. embed-physical-extract (EPE) style and embed-optimise-physical-extract (EOPE) style. The simulation result shows the survivability of constraint in the EPE style retains intact, while it degraded for a large degree in the EOPE style with the best propagation probability of 49.53%. The result gives evidence of how constraint propagates in the physical design of a circuit.

Today, batteries are widely used in mobile devices, vehicles and military applications. Batteries meet the energy needs of the equipment on the vehicle in military vehicles which is one of the application areas. During the military vehicle is stationary, the vehicle engine must not work for camouflage. Therefore, it needs a battery charge circuit. Controlled charging/discharging of the batteries is very important for the cycle life and safety of the batteries. Many conventional battery chargers units charge it without considering the battery temperature. In this study, adaptive battery charging method design and circuit is taken into consideration, considering the battery temperature. The adaptive battery charging algorithm has been applied to charge the batteries of military vehicles and in accordance with military standards (MIL-STD-1275-E voltage surges and MIL-HDBK-454B electronic equipment standard). In this study, experiments with different charge rates have been made and conventional constant current and constant voltage method and proposed adaptive battery charging method result are compared. Experimental results show that the battery temperature decreases 15°C with the proposed charging method. This adaptive battery charging method has been shown to prevent overheating of the battery.

Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple-valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1-qudit and n-qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1-qudit gates and 2-qudit Muthukrishnan–Stroud gates. The efficiency of their proposed circuits was reported.

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit designs. The circuits in QCA have been extensively studied, which suffer from negative impacts due to the limits of the manual design process, even for a modest complexity. In the process of QCA circuit design, the problems caused by clock distribution and long transmission lines have to be considered. In order to solve such problems, some researchers have proposed several clock schemes and expected to realise electronic design automation. These clock schemes, however, have drawbacks; the most important one is the limitation of flexibility on designing complex circuits. In this regard, this study proposes a convenient, flexible, and efficient (CFE) clocking scheme by using diamond structures for clock zones, each of which has the same neighbouring clock zone and four information transmission directions. It has main advantages of existing clocking schemes and can commendably increase the flexibility in circuit design process. In order to show the suitability of the proposed CFE scheme using standard clock mechanism in QCA, several types of circuits proposed in this study reveal its advantages in comparison with an existing state-of-the-art clocking scheme.

A multiple cascode flipped active inductor (MCASFAI) is proposed to determine the degrees of freedom in cascode flipped active inductor (CASFAI). The inductance value of CASFAI is dependent on negative transconductor in gyrator network. This finding is in contrast to the finding that has been reported in the literature, on the degrees of freedom in CASFAI. As the transconductance of negative transconductor increases, inductance decreases, and quality factor increases. The MCASFAI proposed in this study is designed to enhance both inductance and quality factor of CASFAIs. Analytical modelling is done to determine the design parameters that affect inductance and quality factor in CASFAI. Verification is done using Cadence Virtuoso in 180 nm process. Bandpass filter based on the proposed MCASFAI is designed to operate at 2.45 GHz centre frequency with a bandwidth of 80 MHz. The designed filter attains a dynamic range of 162 dB-Hz and figure of merit of 153 dB-HZ/mW, which is comparable to the bandpass filter designs reported in the literature.

Learning algorithms and devices are an essential part of neural networks and neuromorphic architectures. Astrocyte, as an important element in the learning of neural networks, is believed to play a key role in long-term synaptic plasticity and memory. In addition, recent experimental observations indicate that astrocytes are active elements in learning in complex networks. In this study, the authors propose a new analogue astrocyte circuit that consumes fewer numbers of transistors compared to its previous counterparts. The authors then use this astrocyte to design a novel analogue circuit to implement a stop-learning mechanism in a spike-based learning algorithm and present its neuromorphic very large scale integration (VLSI) simulations. Experimental results demonstrate that the designed circuit can precisely implement the learning mechanisms shown by previous studies implementing spike-based learning rules without astrocyte. The proposed circuit proposes the first analogue stop-learning control algorithm that uses astrocytes. It has been designed and simulated in Taiwan semiconductor manufacturing company (TSMC) 0.35 µm complementary metal-oxide semiconductor (CMOS) technology.

This study presents a novel hybrid memristor (MR)-complementary metal–oxide–semiconductor-based flash analogue-to-digital converter (ADC). The speed and efficiency of the ADC are important aspects that can significantly affect the overall system performance. The flash ADC is considered the fastest type of ADCs; however, its performance is affected by the resistor mismatch. The proposed flash ADC is the first to use tunable MR to replace conventional resistor to generate accurate reference voltages. This is achieved by utilising the highly analogue behaviour observed in multi-state MR devices fabricated and tested by the authors' group. The electrical parameters of the devices have been extracted by device characterisation, then the voltage-threshold adaptive model (VTEAM) has been used to develop a correlated mathematical and Simulation Program with Integrated Circuit Emphasis (SPICE) device model. The proposed MR-based flash-ADC design solves the issue of resistor mismatch that results in encoding errors by the ability to tune the MR resistance value post-processing. Moreover, being a nanoscale component, the usage of MR significantly improves the area efficiency of the target ADC. Furthermore, the proposed design has improved the ADC transfer function characteristic and has lower differential non-linearity and integral non-linearity errors compared with the conventional design.