Here, the authors propose an analytical model to evaluate the performance of an advanced trigate MOSFET structure called trapezoidal trigate MOSFET on silicon-on-nothing (TTMSON). The model is based on the solution of Poisson's partial differential equation in three dimensions. The expression for potential distribution has been used to model other device parameters like electric field distribution, quantum inversion charge, and threshold voltage. The TTMSON device immunity to various short channel effects (SCEs), such as drain-induced barrier lowering (DIBL) and sub-threshold swing, has been examined. A detailed analysis of the gate and channel engineering techniques like dual material gate, graded channel, and dual material gate with graded channel has also been carried out to choose the best device structural configuration for enhancing the device performance and mitigating SCEs in nano-regime. In addition, the effect of inclination angle on different performance parameters has been considered. The proposed analytical model of TTMSON has been verified by comparing the model results with the simulation results using the numerical device simulator ATLAS.

Advanced encryption standard (AES) crypto-algorithm design can be implemented in software and hardware. No known attacks are available that can break the AES with brute force or cryptanalysis in finite time. However, when the AES is implemented in hardware, test infrastructure such as scan chain, stimuli decompressor, response compactor and built-in self-test (BIST) are included in the normal design for making the crypto-chip easily testable after manufacturing. This test infrastructure is highly susceptible to attacks. The attacker may misuse the scan-chain content for the retrieval of secret key from AES hardware. In this study, the authors investigated scan-chain attack based on different distributions of key-related flip-flops of AES hardware implementation with X-tolerant response compactor-based test infrastructure. The modular exponentiation security scheme as a counter measure against test infrastructure attacks is proposed. In this study, the statistical security analyses are performed with and without the proposed countermeasure in case of AES hardware followed by X-tolerant test response compactor. The experimental result shows that the proposed countermeasure thwarts the attack with almost constant rate for different distributions of key-related flops in the scan-chain, and hence it is not dependent on the nature of scan-chain architecture design.

In this study, a broadband high-power amplifier with resistive harmonic matching is introduced. The analytical formulations for the drain voltage, output power, optimum load resistance, and efficiency are derived for this type of amplifier under class-B bias conditions. The design is based on a linear model of a laterally diffused metal–oxide–semiconductor transistor. In contrast to the conventional linear method that is based on an equivalent output circuit, the output matching circuit is designed in the presence of the dependent current source and intrinsic elements of the transistor. The design technique permits a broadband amplifier to be realised without load–pull measurement. The broadband power amplifier is intended for operation in the frequency range of 30–1000 MHz and covers the very high-frequency (HF) and ultra-HF bands. The power amplifier delivers 100 W to a 50 Ω load with efficiencies of 38–56%. To validate the design concept, the measured performance of the power amplifier is compared with simulations that incorporate a non-linear model of the transistor. The power amplifier is not driven into saturation and exhibits 2nd and 3rd harmonics of <−20 and <−10 dBc, respectively.

Precise keeper control of domino logic circuit can significantly increase the speed of operation. However, the positive feedback gain associated with the feedback keeper circuit unduly increases the delay variability. Here, a novel high-speed clock delayed dual keeper (CDDK) domino circuit is presented, which aims at reducing the delay and lower the impact of loop gain on delay variability. In CDDK domino structure, the keeper circuit comprising of two keeper devices is disabled during the initial evaluation phase. This significantly reduces the contention current and thereby the operating speed of the circuit is enhanced. The simulations of the circuits have been carried out for various metrics and the results have been analysed. Furthermore, the Monte–Carlo simulations carried out for 2000 runs on a 128-input OR gate using CDDK structure demonstrate reduced delay variability characteristics due to smaller loop gain of the CDDK domino structure against the conventional domino logic style. The enhanced speed of operation due to reduced contention current is demonstrated. The results are validated through comparison against the conventional domino logic counterpart circuits. The analyses of the circuits are performed using industry standard full-suite Cadence® tools using 90 nm technology library.

Microbial fuel cells (MFCs) are an important renewable energy source for underwater sensors. However, bioturbation problems cause short circuits in MFCs. Using distributed multiple anodes can effectively solve this problem. This paper presents a new power converter design that automatically detects the impaired anodes and disconnects them from the rest of the system for better energy efficiency and robustness. The evaluation was made by using 90 nm CMOS technology. The proposed power converter provides 42% more end-to-end efficiency than conventional design under the worst-case scenario.

This study presents a new energy-efficient design for static random access memory (SRAM) using a low-power input data encoding and output data decoding stages. A data bit reordering algorithm is applied to the input data to increase the number of 0s that are going to be written into the SRAM array. Using SRAM cells which are more energy-efficient in writing a ‘0’ than a ‘1’ benefits from this, resulting in a reduction in the total power and energy consumptions of the whole memory. The input data encoding is performed using a simple circuit, which is built of multiplexers and inverters. After the read operation, data will be returned back to its initial form using a low-power data decoding circuit. Simulation results in an industrial and a predictive CMOS technology show that the proposed design for SRAM reduces the energy consumption of read and write operations considerably for some standard test images as input data to the memory. For instance, in writing pixels of Lenna test image into this SRAM and reading them back, 15 and 20% savings are observed for the energy consumption of write and read operations, respectively, compared with the normal write and read operations in standard SRAMs.

A feasibility study of a carrier recovery technique based on a feed-forward controlled leakage transmission carrier is presented. The study proposes a receiver topology and verifies its feasibility by means of the system-level simulations. The results of the study indicate that the proposed technique is theoretically modulation-independent and can be used with each modulation format. To demonstrate a practical feasibility, a BPSK receiver topology is proposed and based on it a demonstrator chip is implemented in a SiGe 0.13 μm heterojunction bipolar transistor technology. To reduce the complexity of the integrated receiver and to sustain low risks at the first production run, the receiver was implemented as all-resistive. The carrier recovery circuit on the chip comprises a static frequency divider and a -band phase-locked loop with quadrature outputs. A direct-conversion sub-harmonic mixer plays the role of a E-band demodulator. The proposed technique can be used in various high baud rate communication applications, saving on the computing power of the digital process.

In this study, a multiphase fractional phase-locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non-idealities of the phase-frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non-idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from −36 to −66 dBc through phase correction and control voltage filtering.

In this study, the authors will investigate the insertion loss (IL) of the broadband 8-way power combiner used in their millimetre-wave power amplifier (PA) design. By treating this combiner as impedance transformer under resistor-capacitor (RC)-loading condition, both the characteristic impedance and electrical length of the constituting metal lines can be obtained, where the much shorter line length suggests wider bandwidth and lower IL. However, proper loss analysis must take into account the multi-reflection of voltage wave along these mismatched transmission lines, i.e. the use of the power attenuation expression is just not accurate enough. With their derived equations, it shows that the IL of their proposed 8-way combiner can be as low as 0.92 dB at 94 GHz, which is much smaller than the 1.5 dB for the conventional quarter-wavelength combiner. Mathematics for the IL of the drain-bias shunt stub and the output DC-blocking capacitor has also been derived. As a demonstration, a 77–110 GHz 40 nm-complementary metal–oxide–semiconductor PA made of cascode transistors is then designed that has more than 18 dB gain, and its OP1 dB is around 13 dBm across the whole frequency range.

In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.

Here, a comprehensive study of the gate-all-around silicon nanowire field effect transistor (FET) (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of air as spacer dielectric, on analogue/RF behaviour of the device. Parasitic capacitances in nanoscale devices contribute a dominating role in overall device capacitances. Introducing air as spacer dielectric () in source/drain underlap region, device parasitic capacitances deteriorates, which improves the overall capacitances. Thus, the analogue/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low-power high-frequency operations. For targeting low power applications, FOMs are elicited at . It is perceived that intrinsic gain of the device is almost unaltered for distinct spacer dielectric ( and air). Frequencies like cut-off frequency () and maximum oscillation frequency () of air spacer dielectric-based underlap GAA-SNWTs are enhanced by 2.92 times and 3.11 times, respectively, when contrasted by the spacer-based GAA-SNWTs. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).

This study presents a 77 GHz receiver (Rx) front-end implemented in TSMC 65 nm complementary metal oxide semiconductor (CMOS) process for the application of automotive radar. This Rx front achieves high linearity, low noise figure (NF) and low local oscillator (LO) power level in compact silicon area. The Rx front-end includes a low-noise amplifier with transformer-feedback technique to improve the bandwidth and linearity, a balun, and a double-balanced mixer with transformer coupling. These techniques allow for compact design and high-linearity. The measurement results have demonstrated a conversion gain of 6.1–9.1 dB over the frequency range of 68.9–80.2 GHz, an NF of 7.8–9.1 dB over the range of 76–81 GHz, and LO-radio frequency isolation of 55–60 dB over 60–90 GHz. The input −1 dB compression point is measured to be −16.8 dBm at 79 GHz. The core silicon area of the Rx front-end is 0.165 mm² excluding pads. The Rx front-end consumes 18 mW from a supply of 1.0 V.

In this study, the authors have presented a simple but robust routability-driven placement for the mixed-size designs. The proposed technique is implemented through (i) look-ahead legalisation-based global placement, (ii) congestion removal and (iii) detailed placement stages. A balanced clustering technique has been proposed to group the circuit blocks into clusters based on the types of circuit blocks and their connectivity. A 0-1 integer programming-based global placement method is framed, which performs look-ahead legalisation. A new site information table concept is introduced to keep the information about each placement cell. Based on the divide conquer strategy, placement area is divided into a region to reduce problem size. A force-directed method has been conceived to select an appropriate region for global placement for the blocks of a cluster. A new congestion removal approach substitutes the legalisation stage to remove circuit block congestion and pin density in different regions. Finally, a gain-based strategy has been introduced for routability-driven detailed placement. The proposed technique is implemented and tested on ICCAD 2012 benchmark circuits. It achieves 1.92 and 0.13% improvements in terms of half perimeter wirelength and routing congestion w.r.t. recent placers.

The consumer electronics markets have increased the demand for high-speed and low-power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel-prefix adders, exhibit high-power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade-off between the delay and power-consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel-prefix adders the least-significant carries are produced much sooner than the most-significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least-significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least-significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65-nm-TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area-delay-product in comparison with state-of-the-art wide-operand adders.

This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Field-programmable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

Biology-inspired neural computing is a potential candidate for the implementation of next-generation intelligent systems. Memristor is a passive electrical element with resistance-switching dynamics. Owing to its natural advantages of non-volatility, nanoscale geometries, and variable conductance, memristor can effectively simulate the synaptic connecting strength between the neurones in the multilayer neural networks. This study presents a kind of memristor synapse-based multilayer neural network hardware architecture with a suitable training methodology. Specifically, a novel dual-complementary metal–oxide–semiconductor/memristor synaptic circuit is presented, which is capable of performing the negative, zero, and positive synaptic weights via controlling the direction of current passing through the memristors. Then, the neurone circuit synthesised with multiple synaptic circuits and an activation unit is further designed, which can be utilised to constitute a compact multilayer neural network with fully connected configuration. Also, a hardware-friendly chip-in-the-loop training method is provided during the network training phase. For the verification purpose, the presented neural network is applied for the realisation of single image super-resolution reconstruction.

In this study, a non-linear compact model for I–V characteristics of FinFETs is presented. The model is developed using the profile of drifting carriers, which plays an important role in determining the device characteristics. A mobility model which incorporates the effect of applied potentials is developed and is used to predict the I–V response of the device. Particle swarm parameter extraction technique is engaged for optimum model applications. It is demonstrated by using the experimental data reported in the literature, that the proposed model can predict the I–V characteristics of FinFETs fabricated using Si and GaN materials having gate lengths ranging from 0.05 to 1 μm.

This research study investigates electrical performance of the multilayered organic light-emitting diode (OLED) with a focus on the role of charge injection, transport and emission layers. Device parameters; luminescence and current density are extracted using Silvaco ATLAS numerical device simulator and validated through the fabricated experimental results with a minor deviation of 3%. Furthermore, a mathematical model is applied to extract other device parameters such as electric field, charge carrier mobility, concentration and current density. Additionally, the multilayered device architecture is critically analysed through cut line methodology to better comprehend the internal device physics in terms of hole-electron mobility, concentration and their recombination. Subsequently, the performance parameters extracted using analytical model are compared with the results of internal analysis and a close match is observed. These results prove the Poole-Frenkel mobility-dependent behaviour in the OLEDs that varies following electric field. Analyses also highlight high electron and hole concentrations in the vicinity of the emission layer as a reason of high luminescence in the multilayered OLED, directly following the Langevin's theory of recombination in organic semiconductors. These analyses highlight the impact of different layers in the OLEDs and thus open up new horizons to further performance improvement in these devices.

This article proposes a new wideband active power splitter design where the gain cells along the input transmission line are arranged in interleaf rather than the conventional parallel style, thus the circuit's high-frequency performance can be greatly improved. Both theoretical analysis and circuit simulation have been carried out; as a demonstration, parallel and interleaf active power splitters are designed using 0.1 μm GaAs pseudo-morphic heterostructure field effect transistors (GaAs pHEMT) process and measured on-wafer. The results clearly indicate the superiority of the interleaf topology. A 40 GHz interleaf active power splitter in 90 nm complementary metal-oxide-semiconductor (CMOS) is then presented where the magnitude and phase imbalance between the two output ports are 0.15 dB and 2.6° at 20 GHz, and 0.16 dB and 14° at 40 GHz. The output-port isolation is better than 30 dB across the whole frequency range.

A dual input DC–DC converter with dual boost and integrated voltage multiplier cell operating at duty cycles larger than 0.5 is a necessity to achieve a high voltage gain for energy systems possessing two independent renewable energy resources. Output voltage regulation during load changes and input disturbances is the requisite of an energy system, which is achieved by the implementation of a suitable control action, which further requires the dynamic model of the converter. The modelling of this higher order converter with overlapping switching signals is complicated. The small-signal transfer function model based on state-space averaging followed by small-signal linearisation is verified using MATLAB and powersim (PSIM). The output voltage to duty cycle transfer functions significantly contributes to representing the converter dynamics from which its right-half s-plane zero is analysed. Since it is a non-minimum phase system, a dual loop control strategy is adopted. Voltage regulation and active current sharing are ensured from the simulation and experimental responses of the uncompensated and compensated systems. Further, from the derived integer-order converter model a fractional controller is designed and its dynamic response is compared with the traditional controller. A 200 W prototype of the converter is developed, and the control is implemented using field-programmable gate array.

This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12-bit 200 MS/s replica driving pipelined analogue-to-digital converter (ADC). Based on the noise design strategy with the target effective number of bits = 10.5-bit, the overall dynamic performance degradation by KT/C noise and thermal noise by an amplifier is alleviated by removing the front-end sample-and-hold (S/H) circuit, and the transconductance (g _m) of the inner source follower is maximised by increasing the current and threshold voltage (V _T) reduction. Replica input sampling networks are designed for the first-stage sub-ADC and the first-stage MDAC with different aspect ratios to minimise the sampling skew for the S/H-less architecture. A prototype 12-bit 200 MS/s ADC is fabricated in a 65 nm complementary metal oxide semiconductor. The measured spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) at a 1.0 MHz input signal is 82.6 and 65.6 dB, respectively, and SFDR and SNDR at the Nyquist (=99.0 MHz) input are 77.3 and 58.6 dB, respectively. The ADC core and the reference driver consume 53.9 and 13.2 mW, respectively, at a 1.2 V supply voltage.

The authors have proposed a robust linearisation method for determining the angles of sinusoidal signals generated by gratings. This scheme solves the problem of non-linear subdivision by compensating sinusoidal signal. The conventional coordinate rotation digital computer (CORDIC) algorithm is optimised by double-rotation iteration, and the calculation accuracy of arcsine and arccosine functions is improved. A pipeline preprocessing circuit based on the CORDIC is designed for the signal compensation and digital subdivision. The two processes are implemented on a field-programmable gate array chip, which exhibits a wide input range and good dynamic response. A theoretical analysis using stable signals from a function generator verifies that the subdivision system achieves the ideal subdivision effect. The subdivision system is further applied to an angle-measuring device for a 16,384-line circular grating. The results of subdivision exhibit good linearity for the grating moiré signal. Compared to the angular measurement by a laser interferometer within the three grating lines, the angle-measurement accuracy of ±0.000138° (0.5″) and the relative error is ±0.63% over a travel angle of three grating lines. Notably, the measurement error of the subdivision system is only half of that in a similar commercial product (MicroE system).

The authors investigate and physically analyse the effects of the angle of grooving (θ) on various analogues and RF parameters of InAs-channel quantum well MOSFETs with raised source/drain architecture at a 14-nm gate length. Moreover, harmonic distortion analysis is performed to examine the linearity and distortion of common source amplifiers built with such transistors. The findings reveal that the device with θ = 20° exhibits significant improvement in transconductance efficiency (g_m/I_DS ), output resistance (r_d ), and voltage gain (A_v ) while showing degradation in transconductance (g_m ) compared to the corresponding parameter with θ = 90°. Furthermore, the obtained results manifest that the total harmonic distortion drops to −47 dB for an amplifier built with the device having θ = 90° compared to −22 dB obtained with θ = 20°. Notably, as the angle of grooving increases from 20° to 90°, the gain bandwidth of the amplifier improves by 232% while the peak gain falls by 40%.

This study proposes an adaptive impedance-matching network with tremendously reduced dimensions and presents its fabrication process. The proposed radio-frequency micro-electromechanical system (RF MEMS) device is based on a coplanar waveguide design and relies on suspended bridges for impedance tuning. The tuning is controlled by a variable applied DC voltage to the bridges. Preliminary tests validate the device's operation mechanism, and simulations were performed on both the mechanical aspects of the device (bridge gap manipulation) and tuning capabilities. This device presents the possibility of operating in a wide band of frequencies, namely [1–6] GHz, and for load impedances in the interval of [30–90] Ω for the real part and [−10–30] for the imaginary part. The device's resonant frequency and its bandwidth can be modified easily by changing the bridge gap in the RF MEMS.

A new tubular field effect transistor (FET) device named silicon nanotube tunnel field effect transistor (Si-NTTFET) has been proposed which is emerged out of structural engineering and the gate dielectric engineering. The proposed structure offers better immunity towards short channel effects (SCEs) because of the combined effect of minimal doping at the drain side and control of channel region due to the double gate. The tunnelling probability is also improved due to narrow energy band variation. The high k dielectric material such as enhances the ON current by a factor of 3 and 14 as compared to and gate dielectric, respectively.