Here, the authors show that an asymmetric cross-coupled oscillator can be used to achieve independent-phase tunable outputs. In particular, a third-order cross-coupled oscillator, with non-balanced loads, is studied and expressions for its start-up condition, oscillation frequency, phase-shift between its two outputs as well as their amplitude ratio are derived. From these expressions, it is found that independent tuning of these design specifications is possible and a voltage-controlled phase-tunable oscillator can be achieved. As a consequence of the non-balanced loads, the tail biasing current is not equally split between the two cross-coupled transistors. However, a design procedure that enables the equal splitting of the current is proposed and validated. Simulations of a prototype in a CMOS process are given and experimental results with discrete transistors verify the correctness of the theory.

This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of- Merit (FoM _W ) of 33 fJ/Conv-Step and Schreier FoM _S of 171.2 dB.

The importance of security in communications has made cryptography one of the most important research for designers. Montgomery modular multiplication is one of the best methods used in cryptosystems. These multipliers can be implemented in different ways including digit-serial architecture. The digit-serial multiplier is an efficient structure for low power and high-speed applications. The architecture of digit-serial multiplier can benefit from the advantage of both serial and parallel structures. This study presents a new digit-serial Montgomery modular multiplier architecture, which takes up less area by reducing internal blocks of the structure. The latency and design complexity of the proposed digit-serial Montgomery multiplier is less than many other similar designs. The critical path delay of the proposed architecture is reduced compared to similar works. The proposed circuit has the flexibility to be used in a large number of bits and can be used for any size of the digit. The simulation results of the proposed multiplier are presented.

An oscillator scheme based on the degenerate band edge (DBE) in a periodic, double-ladder resonant circuit made of lumped elements is proposed for the first time. The circuit exhibits a DBE in the dispersion diagram of its phase-frequency eigenstates and possesses unique resonance features associated with a high loaded Q-factor resonance, compared to a single-ladder circuit. This oscillator is shown to have an oscillation threshold that is half that of a single LC ladder circuit having the same total quality factor, and thus is more robust than an LC oscillator in the presence of losses. Moreover, the double-ladder oscillators have a unique mode selection scheme that leads to stable single-frequency oscillations even when the load is varied. It is also shown that the output amplitude of the double-ladder oscillator is much less sensitive to the output loading compared to single-ladder oscillators. The authors show the analysis and design of such oscillators that potentially lead to enhancing the efficiency of RF components and sources.

Data security is essential for the proliferation of the Internet of things and cyber-physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of high-performance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex-5 XC5VLX110T (ff1136-1) field-programmable gate array device of ML-505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource-efficient, high-performance and suitable for lightweight, latency-critical and low-power applications in comparison with existing architectures.

In recent years, the use of wireless power transfer (WPT) has gained momentum in electric vehicle charging. To design the WPT system, three-dimensional (3D) finite element method (FEM) is used for mutual inductance calculation, and the system performance is evaluated using a circuit simulator. The use of 3D FEM makes the initial design a tedious process. Hence, there is a need for a reliable analytical model which can be used in the preliminary design process. This work proposes a mathematical model of a series–parallel (SP) compensated WPT system that can determine the mutual inductance and the system parameters such as voltage, current, power, and efficiency for different misalignments. The mathematical model consists of electromagnetic and steady-state models. This model can be used to analyse the component stress of SP compensated WPT system. The results of the mathematical model are verified experimentally. Thus, the proposed method can be adopted in the initial design process of SP compensated WPT system.

As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticality-based statistical gate sizing method is presented for improving timing yield of the circuit.

The authors propose circuit techniques to implement integrated continuous-time filters for low voltage and low power applications. A fourth order G _m-C filter and a fifth order active-RC Chebyshev filter are used as test vehicles to validate the ideas. Basic building blocks are bulk driven transconductors. G _m-C filter and active-RC filter offer bandwidth of 1 MHz and 750 kHz, respectively while exhibiting a good figure of merit thus ensuring that the designs are energy efficient. Both the filters, fabricated on the same chip in 180 nm CMOS technology, operate on 0.5 V power supply. They offer a dynamic range of 45 and 46.6 dB, respectively.

This study presents an adaptive data-transition decision feedback equaliser (DT-DFE) with a sign³ least-mean-square (LMS) tap adaptation. Commonly used data-state (DS) DFE suffers from reduced vertical eye-opening when consecutive 1's or 0's are encountered. The proposed DT-DFE performs DFE only when a data transition is detected. It boosts the eye-opening of the high-frequency components of data without attenuating the low-frequency components of data whereas DS-DFE boosts the eye-opening of the high-frequency components of data at the expense of the attenuated low-frequency components of data. The reference voltages of DS-DFE is tap-dependent whereas those of DT-DFE are tap-independent and are obtained by conveying consecutive 1's and 0's to the channel in a training phase. The proposed DT-DFE utilises loop unrolling to detect the occurrence of data transition. The performance of the proposed DT-DFE is compared with that of DS-DFE using two 5 Gbps backplane serial links designed in a TSMC 65 nm CMOS technology. Simulation results demonstrate that the eye-opening of the link with DT-DFE is 1.54 times that with DS-DFE. The vertical eye-opening of the link with DT-DFE activating tap adaptation on two consecutive state transitions of opposite polarities is 1.2 times that that activates tap adaptation on single state transition. The proposed DT-DFE is less sensitive to process uncertainty whereas DS-DFE is prone to process uncertainty with severely deteriorating performance.

A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.

This study presents frequency upscaling as a technique for developing error resilient arithmetic designs in approximate computing whereby the input signal frequency of the circuit is upscaled beyond its largest operating value in generating errors in the arithmetic operation while speeding up the computational throughput. This study initially presents the mathematical modelling of frequency upscaling for both exact and inexact full adders. An exhaustive simulation and evaluation of 4 and 8 bits subtraction followed by addition of two images and approximate discrete cosine transform (DCT) is pursued using exact and inexact circuits when subjected to the proposed technique. The results estimated using the proposed model show good agreement with the simulation results. The normalised mean error distance of subtraction using an inexact circuit is close to the exact value for different technology nodes. The peak signal-to-noise ratio (PSNR) results for the addition of two images show that the inexact full adder achieves a higher output image quality than the exact circuit when the frequency is scaled up. Also, in an approximate DCT, the input frequency of an inexact full adder can be scaled up significantly higher than an exact full adder without a significant decrease in PSNR value.

For enhancement of and in tunnel field-effect transistors (TFETs), it is important to choose novel materials and structures. Here, the authors design a hetero-dielectric buried oxide vertical TFET (HDB VTFET) and its device characteristics has been investigated. This proposed device reveals the tremendous improvement in terms of sub-threshold slope, drain-induced barrier lowering, on-current and suppresses the ambipolar behaviour up to V _gs = −1.0 V by maintaining very low off-current. Hence, the concept of hetero-dielectric buried oxide (BOX) and two metal electrodes having different work-functions are used here to obtain better results in terms of the current driving capability, steep subthreshold slope (SS) and drain-induced barrier lowering (DIBL). This device is a promising candidate for low-power consumption applications.

This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the anti-imaging filter. Different data scheduling and projection operations were developed. Nine systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation. Field-programmable gate array implementations for the conventional and proposed designs confirm that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than the conventional design.

In this endeavour, the fruition of a resurrected tunnel field effect transistor has been investigated incorporating the idea of strained channel engineering along with the implementation of dielectric modulation technique. A non-homogeneous pattern of gate oxide layer is considered with hetero-dielectric architecture at the front gate and linearly graded oxide at the back gate. The buried oxide (BOX) thickness is kept intentionally double that of front oxide one to reduce electric field lines penetrating from drain to source, thus minimising fringing field effect. The surface potential function has been deduced with the help of 2D Poisson's equation assuming appropriate boundary conditions. Lateral electric field and hence total electric field have been computed from channel potential to study tunnelling efficiency, hot carrier effect and drain induced barrier lowering for the aimed device. Finally drain current has been derived with the help of Kane's model upon integration of band-to-band tunnelling rate and the results have been compared with previously published reports to corroborate the eminence of the proposed model. All analytical corollaries are in adroit amity with Silvaco ATLAS simulated data for avowal of the developed modelin terms of sublime short channel behaviour.

In this study, an integrated synchronous data acquisition subsystem for high-speed dual-channel ultra-wideband ground penetrating radar (GPR) system is designed and tested. Factors that could cause data missing and asynchronisation are analyzed. According to timing sequence, a field-programmable gate array-based onboard digital control module is integrated to synchronise the data acquisition and data storage subsystems. By applying simultaneous multi-buffer acquisition and readout mode and multi-threading configuration, as well as the critical section control and queue storage structure, the GPR data throughput is considerably improved. For the practicality of this system, a smart End-of-Job control design is performed between different threads to control data acquisition. By using different performance indexes, receiver operation characteristic curve, maximum scan rate, and the rebar detection experiment demonstrate the superiority of author's method.

Design of a novel phase frequency detector (PFD) has been presented here. The innovative advantage of the proposed structure is its improved dead zone performance due to the architectural simplicity which is a combination of static and pass transistor logic (PTL)-based latch configuration. Due to low latency from inputs to the outputs, the operating frequency of the proposed circuit is high while its power consumption is very low. Analytics along with simulations have confirmed the correct behaviour of the designed circuit. For better evaluation of designed architecture advantages, two of the last reported works have been redesigned and simulated along with the proposed PFD. The post-layout simulation results using HSPICE with TSMC 0.18 µm CMOS technology and 1.8 V power supply demonstrate the operating frequency of 1 GHz for the designed circuitry while the power dissipation is 277 µW and the measured dead zone is as an enormous enhancement over previous works.

The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip–flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

This article proposes a wideband ΔΣ fractional-N frequency synthesiser (WBFS) for software-defined radio application. The frequency synthesiser has two modes: the regular mode with low phase noise performance and the low-power mode for the low-power applications at lower frequency band. The authors also propose adjustable replica (AR) bias circuit for the frequency selection multiplexer (FSMUX) in the divide-by-two divider chain to optimise the power consumption at different frequencies while keep the output swing constant at different bias current to achieve robust operation. The FSMUX is implemented in differential structure instead of the widely used quadrature structure to reduce power and area especially at high carrier frequency. Implemented in 65 nm CMOS process with a 1.2-V supply, the WBFS generates frequency from 0.1 to 5 GHz. The maximum power at regular and low-power mode is 21 and 10.2 mW, respectively. The phase noise is −120.3 dBc/Hz at 1 MHz offset (2.75375 GHz) at regular mode and −122.8 dBc/Hz at 1 MHz offset (1.3525 GHz) at low-power mode. Thanks to the differential FSMUX with the proposed AR bias circuit and the low-power mode, the WBFS power is significantly reduced, compared with that of the prior WBFS with comparable frequency range.

The low power energy harvesters need efficient single-stage direct ac–dc conversion evading diode bridge rectifier. An active rectifier circuit is proposed for piezoelectric energy harvester working on the principle of the buck–boost converter. The active rectifier circuit provides dual output with a reduced number of components. The analysis of the active rectifier is carried out, and expression for the optimum duty cycle is derived for maximum power extraction. The active rectifier configuration is extended for connecting multiple piezoelectric energy harvesters, and maximum power extraction is achieved through time multiplexed switching of energy harvesters. Proposed active rectifier topology is validated through simulation and experimentation. The results demonstrate that the harvested power is improved by the factor of 1.4 and 3.2 for single input and multiple input configurations, respectively, as compared to the power harvested using dual output rectifier. The charging time of the supercapacitor is reduced by 17 min while charging through the single input configuration and 15 min while charging through the multiple input configuration of the proposed active rectifier circuit.

A second-order lowpass Butterworth filter with tunable bandwidth capable of offering a dynamic range of 91.86 dB operating on a supply voltage of 1.8 V is presented. The proposed filter is based on a sub-threshold source follower. The transistor bias currents are switched to enable the bandwidth tuning in the range 4–100 Hz. A proportional to absolute temperature (PTAT) current reference circuit helps to keep the bandwidth intact across process, voltage and temperature variations. The filter, designed in 0.18 µm standard CMOS process, consumes 25.9 nW making it a potential candidate for portable biomedical applications.

This study reports the design and analysis of novel step structure RF micro-electromechanical system (MEMS) switch for low pull-in voltage, low insertion loss and high isolation by using uniform single meander. The central beam of the membrane is designed with 0.5 µm lower than the side beams to form a step-down structure which reduces the pull-in voltage. Stress analysis, electromechancial, switching time, quality factor and RF analysis have done to understand the behavioural characteristics of the proposed step-down switch. The analysis has been carried out for different beam and dielectric materials among them switch with gold material exhibits low pull-in voltage of 4.7 V, low insertion loss <1 dB and high isolation of −38.3 dB at 28.2 GHz for silicon nitride. The switch also shows good quality factor of 0.95 for gold material along with high capacitance ratio of 132. The upstate capacitance of 56.8 pF contributes low return loss and made the switch to transmit the signal up to 26.2 GHz and provides 7.2 pF of downstate capacitance to produce high isolation at 26.2 GHz which is efficiently used for K-band satellite applications.

Here, a novel optical micro-electro-mechanical systems (MEMS) accelerometer sensor based on a micro-ring resonator and an elliptical disk is proposed. The designed optical MEMS accelerometer is then analysed to obtain its functional characteristics. The proposed optical MEMS sensor presents an optical sensitivity of 0.0025 nm/g, a mechanical sensitivity of 1.56 nm/g, a linear measurement range of ±22 g, a first resonance frequency of 13.02 kHz, and a footprint of 34 μm × 50 μm. Furthermore, the achieved functional characteristics of the proposed accelerometer are compared to several recent contributions in the related field. According to this comparison study, the present optical MEMS accelerometer can be a suitable device for many applications ranging from consumer electronics to inertial measurement units.