In this study, low-cost and high-throughput hardware implementations of the HIGHT (HIGh security and lightweigHT) and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo . In the proposed structure for implementation of this modular adder, the authors used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimised combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay is reduced by using Karnaugh mapping and further factorisation. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. Implementation results of the proposed architectures in 180 nm complementary metal–oxide–semiconductor technology for different unroll factors are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to other related works.

Datapath macros are essential components of integrated circuits. The high regularity of datapaths allows compact layout design during placement. In some cases, datapath macros are manually pre-designed and pre-placed. However, datapath macros are frequently mixed with other circuits and they need to be extracted to capitalise on their regularity. In this study, the cells of a given circuit are accurately classified based on their size and pin information, and novel connection vectors to represent aspects of the connectivity among the cells have been proposed. By using the connection vectors of the cells, the similarity of connections is evaluated to extract potential datapath stages that constitute functional steps of a datapath. Two new efficient datapath logic extraction techniques (EDLETs) have been implemented based on the connection vectors for extracting potential datapaths in the circuit. One is the procedure-based method, and the other is the machine learning-based method. When compared with state-of-the-art methods, the experiments show that both the procedure-based and the learning-based methods proposed in this study efficiently extract potential datapaths from the Modified International Symposium on Physical Design (MISPD) 2011 Datapath Benchmark Suite. The extraction results of the proposed EDLET can be forwarded to a datapath placement tool for placing datapaths with a regular structure.

Routeing protocol for low-power and lossy networks (RPL) are widely used in dynamic wireless sensor network. Several types of researches worked on RPL and designed hybrid energy-efficient cluster-parent-based RPL, queue utilisation (QU)-RPL, improved RPL, attack detection RPL etc. to support from vulnerable threats, provide efficient routeing and balance dynamic nodes in the network. Previous research findings dealt with certain limitations and problems. In this study, a new coordinative-balanced clustering algorithm is proposed which is enabled to balance destination-oriented directed acyclic graph (DODAG) that is formed in each cluster. Pruning of nodes from DODAG effectively maintains cluster with minimised complexity. This study also resolves the problem of two common security attacks such as distributed denial of service attack (DDoS) and version number attack. Then, enriched-ant colony optimisation is used for DDoS detection and a secure route is chosen to perform data transmission. At the instance of selecting best parent for forwarding data, the authors use residual energy and scoring factor. Scoring factor of each node denotes the legitimacy to be selected as the best parent. Finally, results obtained from Network Simulator 3 indicate better performances on the following metrics: packet delivery ratio, end-to-end delay, node death minimisation, packet loss rate and power consumption.

Bird's eye view (BEV) generation from front-looking video stream is considered an important pre-processing task in various computer vision applications such as driver assistance systems. In this work, hardware implementation of this process using high-level synthesis in Simulink environment has been considered for rapid prototyping under real-time constraints. Traditionally, researchers have employed lookup table-based approaches to circumvent the exorbitant cost of implementing arithmetic modules associated with the perspective transformation. The hardware implementation scheme proposed here, however, demonstrates that a polynomial approximation over the limited domain of the involved operands not only saves precious hardware resources but also provides better fixed-point precision. Synthesis results on Zynq-7000 FPGA show that the proposed circuit reduces the block memory utilisation by 9% compared to the lookup table-based built-in Simulink Vision HDL block. The proposed design evaluates the results in fixed-point format which is essential for subsequent bilinear interpolation to produce high-fidelity output frame, albeit at the cost of 4% increase in DSP48E utilisation. The approximation error of the proposed solution is less than quarter-pixel on average. The proposed hardware has been integrated as an IP core in a hardware-software co-design system. The whole framework is publicly available to facilitate practitioners and researchers.

The line tunnelling and heterojunction are two important techniques to improve the performance of the tunnelling field-effect transistors (TFETs). The TFETs that utilise both of these techniques perform superior to the conventional TFETs. The recently proposed T-shaped TFET (TTFET) is one such heterojunction-based line tunnelling device that is expected to become energy efficient switch. For the first time, a physics-based analytical model for surface potential and drain current of epitaxial layer-based heterojunction line TFET has been developed. The model describes the impact of device design parameters on the electrical performance of the device. The Poisson equation is solved with precise boundary conditions to obtain the surface potential model. Kane's model is used to calculate drain current by utilising surface potential model. A good agreement between Synopsys technology computer-aided design simulation and analytical model is observed with 5.4% error in on current at V _GS = V _DS = 0.5 V, an average error of 5.80% in surface potential and 7.24% in transconductance. Finally, a device design guideline is presented according to the analytical expressions.

The continuous monitoring of cardiac patients requires an ambulatory system that can automatically detect heart diseases. This study presents a new field programmable gate array (FPGA)-based hardware implementation of the QRS complex detection. The proposed detection system is mainly based on the Pan and Tompkins algorithm, but applying a new, simple, and efficient technique in the detection stage. The new method is based on the centred derivative and the intermediate value theorem, to locate the QRS peaks. The proposed architecture has been implemented on FPGA using the Xilinx System Generator for digital signal processor and the Nexys-4 FPGA evaluation kit. To evaluate the effectiveness of the proposed system, a comparative study has been performed between the resulting performances and those obtained with existing QRS detection systems, in terms of reliability, execution time, and FPGA resources estimation. The proposed architecture has been validated using the 48 half-hours of records obtained from the Massachusetts Institute of Technology - Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real time via the analogue discovery device.

This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.

In this editorial, the effect of dual gate underlap has been implemented on ED-TFET and it is named as underlap dual metal gate electrically doped tunnel FET (UL-DMG-ED-TFET). The proposed device has been reviewed in terms of device characteristics and analogue/radio-frequency figure of metrics. By using underlap theory, the authors have resolved the issues of ambipolarity and gate leakage current but somewhat C _gd also increases without affecting the DC performances. Moreover, the authors have implemented the dual gate on the proposed device which helps to improve the DC and RF FOMs. Furthermore, the inversion layer and C _gd inversion along with parasitic capacitances also deliberate on proposed device (UL-DMG-ED-TFET). Finally, the dual gate-underlap provides better DC and analogue/RF performances in comparison over conventional structure.

In two-stage grid-integrated photovoltaic (PV) system, usually a DC–DC converter is employed between the PV modules and the inverter. The dynamic interactions between the DC–DC converter, inverter, and the maximum power point tracking (MPPT) controller may affect the system performances. This study gives an integral procedure to design a stable sliding-mode controller (SMC) based on fixed frequency equivalent control approach to improve the transient response of PV system and to track the reference voltage supplied by the voltage-oriented MPPT controller in the presence of environmental and load perturbations and converter output sinusoidal perturbations imposed by the second harmonic of the grid frequency. The controller consists of fast current tracking inner current loop based on SMC law whose sliding surface is defined by the input capacitor and inductor current and outer PI controller maintains required PV voltage regulation. The superiority of the controller is validated at different operating conditions through PSIM software and its performance is compared with variable frequency hysteresis-based SMC. To check the static and transient performances of the system, various experiments are conducted. The results obtained show very fast transient response in settling time and alleviation of chattering magnitude at various operating conditions.

Reversible computing is one of the most promising technologies in the design of low-power digital circuits, optical information processing, quantum computing, DNA computing, digital signal processing, and nanotechnology. The main purpose of the design of reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. A gate/block is reversible if the number of inputs and the number of outputs are equal and there is one-to-one correspondence between them. Latches are considered as one of the most important digital structures that are widely used as building blocks in the design of sequential circuits. Here, eight new reversible blocks are first offered. Then using some of them, several effective designs of reversible D, T, and J-K latches are proposed. The results of the evaluations indicate that the proposed latches are superior in terms of quantum cost (QC) than previous designs. Moreover, they are very close to or better than the best previous designs in terms of criteria such as gate count (GC), constant inputs (CI), and garbage outputs (GO).

Multiplication is an arithmetic operation that has a significant impact on the performance of various real-life applications, such as digital signal processing, image processing and computer vision. In this study, targeting to exploit the efficiency of alternative number representation formats, the authors propose an energy-efficient scheme for multiplying 2's-complement binary numbers with two least significant bits (LSBs). The double-LSB (DLSB) arithmetic delivers several benefits, such as the symmetric representation range, the number negation performed only by bitwise inversion, and the facilitation of the rounding process in the results of floating point architectures. The hardware overhead of the proposed circuit, when implemented at 45 nm, is negligible in comparison with the conventional Modified Booth multiplier for the ordinary 2's-complement numbers (3.1% area and 3.3% energy average overhead for different multiplier's bit-width). Moreover, the proposed DLSB multiplier outperforms the previous state-of-the-art implementation by providing 10.2% energy and 7.8% area average gains. Finally, they demonstrate how the DLSB multipliers can be effectively used as a building block for the implementation of larger multiplications, delivering area and energy savings.

Here, a new active snubber cell for high-power isolated pulse-width-modulated (PWM) DC–DC converters is proposed. All semiconductor power devices in the proposed converters operate with full soft switching under a very wide load range, and they are not exposed to any voltage and current stress. The main switches turn on with zero-voltage transition (ZVT) and turn off with zero-voltage switching (ZVS). The auxiliary switches turn on with zero-current switching (ZCS) and turn off with ZVS. The theoretical analysis and design procedure for the proposed active snubber cell are carried out in detail and are verified with a half-bridge (HB) converter implementation having 20V output voltage, 50 A output current, and 80 kHz switching frequency. The overall efficiency of the HB DC–DC converter is increased from about 83% in the hard switching condition to about 90% thanks to the proposed active snubber cell.

This article presented a novel digital blind calibration technique of time-skew mismatches for time-interleaved analogue-to-digital converter (TI-ADC). Based on the frequency-shifted and derived operation, the spurious signals could be reconstructed and subtracted from the sampled signal adaptively. The main advantage of the proposed calibration technique is applicable to any channel TI-ADC and could achieve higher performance in comparison with the state-of-the-arts. Numerical simulations and experimental results have demonstrated that the proposed calibration technique could significantly improve the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI-ADC system.

The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

Digital envelope detection, self-correlation and high frequency sampling techniques are proposed for high data rate demodulation of on–off keying signals that are widely used in impulse radio ultra-wideband receivers. The proposed designs eliminate the requirement of complex synchronisation circuit architectures and algorithms. The presented circuits are all digital and can be utilised in the baseband synchronisation. The digital envelope detection and self-correlation methods are implemented in 130 nm complementary metal oxide semiconductor (CMOS) technology and concepts are verified with measurement results. Post-layout simulation results are given for the high frequency sampling technique. Measurements show that the digital envelope detector demonstrates successful operation up to 600 Mbps data rate with 2.1 mW power consumption. The self-correlator consumes 10 mW with 100 Mbps data rate in the measurements. The post-layout simulations results show that the high frequency sampler can operate at 2 mW with 500 Mbps data rate.

Approximate computing can be used in the error-tolerant applications since it can provide meaningful results with lower power consumption. In this study, the authors proposed a novel imprecise 4-2 compressor which is used in the multipliers of image processing applications. Besides the output values, they also consider the pattern distribution to resynthesise the 4-2 compressor in imprecise style. Compared to the precise compressor, the proposed imprecise 4-2 compressor can reduce power consumption and delay by 56 and 39%. Compared to the precise multiplier, the simulation results show that the multiplier which uses the proposed imprecise 4-2 compressor can achieve 33 and 30% improvement in power consumption and delay, respectively. In addition, the image quality of their design is good for human perception because peak signal-to-noise ratio PSNR values are more than 33 and mean structural similarity values are more than 0.99. Even compared to the related imprecise works, their design has a better error rate to improve the quality of images while maintains both the high power efficiency and low circuit complexity.

This article presents a 10-bits low-power successive approximation register analogue-to-digital converter (SAR ADC). The dual sampling technique was applied to the capacitive digital-to-analogue converter (CDAC), and the CDAC structure was constructed using a binary-weighted capacitor array and a C-2C capacitor array, simultaneously. Consequently, the CDAC structure enabled low-power consumption and a small layout area for the proposed SAR ADC. Moreover, the rail-to-rail operation of the bootstrapped circuit enabled the low-voltage ADC to be implemented, thereby improving the non-linearity. A prototype was designed and implemented using TSMC 0.18 μm CMOS 1P6M technology. This design achieved differential non-linearity and integral non-linearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively, and a signal-to-noise-and-distortion ratio of 56.7 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 2 MHz. At a sampling rate of 40 MS/s with a single 1.2 V power supply, the power consumption was 736 μW. The proposed ADC achieved a figure-of-merit of 32.84 fJ/conversion-step. The ADC core occupied an active area of 195 × 241 μm².

Feature extraction is an important function in the speech recognition system. Employing a speech recognition system in low-resource devices (LRDs) have increased significantly in recent years. Implementing feature extraction, which involves complex computations, in LRD is very challenging because LRD has limited energy, storage, and processing power. The optimum design must carefully balance performance metrics, including speed, area, and energy. The objective of this research is to implement and model speech feature extraction design in a field-programmable gate array (FPGA) platform, and to identify the optimum implementation for low-resource devices (LRDs). The novelty of this research is optimising feature extraction implementations using design options such as word size; and developing accurate performance models to enhance future designs. The authors study extensively examines the effect of fixed-point n -bit word size on the design of Mel frequency cepstral coefficients feature extraction in the FPGA implementation. The results show that the performance metrics (area, power, and energy) increase at a slower pace compared with n because the dependency of some blocks (e.g. logarithm) on n is non-linear. For example, increasing n by 50% increases the resource utilisation by 38%, power by 41% and energy by 41%. Models for resources, power, and energy are developed with accuracies of 5.1, 4.5, and 4.3%, respectively. Furthermore, n has a weak impact on timing results and therefore speed is almost similar across implementations. Each bit (in n ) costs 690 logical elements in the area, 2.35 mW in power and 0.55μJ in energy. For LRD, the 32-bit design demonstrates the most optimum design, followed by 48-bit and 24-bit designs.

In recent years, many researches have been conducted on 6T static memory performance improvements and strengthen it against soft error in sub-threshold region. These studies finally result in some SRAM cell designs with the proper performance in bit-interleaving structure and sub-threshold region in cost of more area consumption. This study presents a new bit-interleaving 7T SRAM cell which occupies less area consumption and has a better performance when compared with other 9T, 10, and 12T bit-interleaving cells. The suggested 7T cell is simulated with HSPICE in 32 nm technology and with multi-Vt transistors considering LP, HP, and standard models for HVt, LVt, and SVt transistors, respectively. The simulation results demonstrate the performance superiority of authors’ proposed cell compared with its counterparts. Moreover, the simulation results (VDD = 0.5 V) show the suggested cell in comparison with conventional 6T cell improves read, hold, and write power consumptions 91.42, 91.93, and 68.7%, respectively. Also, cell stability (RSNM) and write margin (WM) parameters improve 172 and 67.2%, respectively.

This study focuses on the topic of model order reduction (MOR) for coupled systems with inhomogeneous initial conditions and presents an MOR method by general orthogonal polynomials with Arnoldi algorithm. The main procedure is to use a series of expansion coefficients vectors in the space spanned by orthogonal polynomials that satisfy a recursive formula to generate a projection based on the multiorder Arnoldi algorithm. The resulting model not only match desired number of expansion coefficients but also has the same coupled structure as the original system. Moreover, the stability is preserved as well. The error bound between the outputs is well-discussed. Finally, numerical results show that the authors’ method can deal well with those systems with inhomogeneous initial conditions in the views of accuracy and computational cost.

The study presents an analytical model for the potential distribution of a drain doping engineered 2D tunnelling field effect transistor (TFET) with splitted drain structure. Hence, tunnelling drain current is derived using this potential distribution. Further, the study analyses the influence of drain doping engineering on all characteristics and parameters of a TFET model. Splitted drain structure exhibits major reduction in ambipolar conduction due to increase of the tunnelling width at the channel-drain junction. Simulation of four different structures of the device consisting of splitted drain region with relative location and doping concentration is executed. The structures are named according to the relative position of the drain: splitted-drain single-gate TFET (SD-SG TFET: total drain is splitted), top-splitted-drain single-gate TFET (TSD-SG TFET: splitted-drain in upper location), Mesial-splitted-drain single-gate TFET (MSD-SG TFET: splitted-drain in middle location), and basal-splitted-drain single-gate TFET (BSD-SG TFET: splitted-drain in bottom location). All the fundamental device characteristics and parameters are analysed for all the four structures, and their merits and drawback are recorded for optimal valuation and detection of better structure. All the proposed structures show improved performance with suppressed gate leakage and ambipolarity than conventional planar TFET. All the simulations are done in Silvaco, Atlas.

This work deals with the development of an open-loop wind turbine emulator to verify the system operation with respect to the wind profile. The emulator consists essentially of a 300 W DC motor powered by DC/DC buck converter which controlled through field-programmable gate array (FPGA) and pulse-width modulation strategy. The motor rotational speed allows to imitate proportionally different wind velocity. A hardware test bench based on the fast prototyping method using MATLAB/Xilinx System Generation (XSG) environment and FPGA board of wind turbine simulator is built to validate the simulation results. Simulation and experimental results confirm the efficiency of the implemented method to make the proposed emulator able to react as a real wind in laboratory.

In this article, the design and development aspects of a compact bio-potential measuring system, named ExGSense, is presented. Two versions of the prototype have been developed; first one can measure 3 + 1 V leads in time-multiplexed fashion, while the other can measure 3 + 1 V leads simultaneously. This article also presents an efficient algorithm for filtering electrocardiogram signals which is required to attenuate the effect of motion artefacts which are inevitable in wearable systems. Further, a user-friendly interface for PC and smartphone has also been developed. By the virtue of an ultra-low noise instrumentation amplifier and the programmability of gain and bandwidth of the bio-signal measuring system, a number of other bio-potential signals like EMG, EOG and EEG have been successfully recorded using disposable, off-the-shelf wet Ag/AgCl electrodes.

This study deals with the design and optimisation of two-stage complementary metal oxide semiconductor low noise amplifier (LNA) for wireless local area network (WLAN) applications. IEEE 802.11n WLAN standard provides up to 600 Mbps speed with 40 MHz channel bandwidth and high throughput. The receiver of these WLAN applications requires LNA with higher gain and minimum noise figure (NF). Elephant Herding Optimisation technique was involved for the first time to optimise the performance of the LNA. The post-layout simulation shows that a maximum gain of 26.7 dB at 2.4 GHz is achieved in the proposed design. Feedforward noise cancelation technique is involved to get a reduced NF of 1.12 dB. The first and second stages are tuned to cover the 3 dB maximum gain bandwidth of 3.2 GHz (from 1.7 to 4.4 GHz). This LNA is designed at 90 nm technology with the supply voltage of 0.5 and 1.2 V, and consumes 8.9 mW of power. Current reuse technology is used to reduce power consumption. The input and output return losses have been found to be −18 and −15 dB, respectively at the targeted 2.4 GHz frequency. Third-order input intercept point of the optimised LNA is −8.1 dBm.

This study presents a new technique based on large signal analysis, to enhance the total harmonic-distortion (THD) in an ultra-low-power operational transconductance amplifier (OTA). The proposed technique is used to implement an ultra-low-power gate-driven and bulk-driven OTA with high linear range. Mismatch and post-layout simulations in 0.13 μm CMOS technology demonstrate that the proposed technique can improve the THD and the dynamic range, without affecting the transconductance tuning and the common-mode control. It achieves a 183 and 640 mVpp linear ranges for gate-driven and bulk-driven OTA, and a 61.8 dB dynamic range at 0.5 V with 26.35 nW power dissipation.