The 2D surface potential and mobility models are proposed for symmetric doped/undoped channel double gate FET (DGFET) device. This is then used in drain current equation obtained by combining Pao-Sah's double integral formula with Pierret–Shields' type current model. The surface potential model and mobility model both are analytic and differently solved for both undoped and doped device. Being an explicit and continuous expression, the drain current model is used to describe the behaviour of the device at below and above threshold condition. Simulations are carried out using TCAD Sentaurus bundle of Synopsis tool. The accuracy of the proposed model is analysed and compared with the simulation result for different channel length and channel thickness value of the device.

The Lempel–Ziv–Welch (LZW) algorithm is an important dictionary-based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries.

Higher variation resilience, lower power consumption, and higher reliability are the three principal design metrics for designing a static random-access memory (SRAM) cell. The most intuitive way to achieve lower power consumption is voltage scaling. However, voltage scaling at nanometre technology nodes leads to degradation in the robustness of the SRAM cell and decreased data stability. It is proved that conventional 6T SRAM fails to maintain its stability in scaled technology, particularly in the deep-subthreshold regime. Furthermore, SRAM cells utilising techniques such as read decoupling, for achieving reliable read operation, tend to increase leakage current resulting in higher hold power, which contributes a major portion to the total power consumption in modern internet of things devices. To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.

Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures. In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its variants, called robust CFTA (R-CFTA), R-CFTA⁺, high throughput CFTA (HT-CFTA), HT-CFTA4R, HT-CFTA8R, and HT-CFTA⁺, are introduced. Proposed approaches exploit the-inherent parallel architecture of AES for employing redundancy at low cost. CFTA and HT-CFTA can tolerate all single permanent and transient faults in the-AES blocks and also all multiple permanent and transient faults in the-same block. R-CFTA upgrades the-fault-tolerant aspect of CFTA and HT-CFTA and it is also able to tolerate all single- and multiple-transient faults in two AES functional blocks during a round. The proof is provided to show the fault masking ability of provided architectures. Furthermore, R-CFTA⁺ and HT-CFTA⁺, which are suitable for high-security sensitive applications are suggested. In addition, the proposed fault-tolerant designs are implemented on both field programmable gate array and application-specific integrated circuit platforms, and their implementation area, frequency, and throughput are discussed and compared with other related works. Moreover, system-efficiency, as an important design metric, is reported for proposed structures.

An input interface for all-spin logic (ASL) circuits is proposed, which is composed of magnetic tunnel junction (MJT) and metal wires that are used for transmitting electrical signals. The proposed input interface can shorten the length of non-magnetic channel and avoid the complex fan-out structure, and is fit for the circuits that need multiple same input signals. Moreover, based on the ASL minority gate and inverter, two kinds of XOR gates are designed. Compared with the XOR gate without input interface, the XOR gate using input interface possesses lower energy dissipation and higher reliability. Using coupled spin-transport/magneto-dynamics models, validity of the input interface and XOR gates are demonstrated. This work provides an interesting approach for the design of large-scale ASL circuits that contain many identical input ports.

Operational trans-conductance amplifiers (OTAs) are an essential building block in analogue and mixed-signal circuits. In this study, a new two-stage class-AB OTA is proposed. The class-AB operation is obtained without extra power dissipation, and without unity-gain bandwidth or noise degradation. The circuit was fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The measurement results indicate 13 dB enhancement in DC-gain and 1.8 times improvement in slew rate compared to its conventional counterpart. Comparison results indicate that the proposed OTA demonstrates better performance than the state-of-the-art designs.

A novel high-isolation leakage carrier cancellation system, which is highly required in the ultra-high frequency (UHF) radio frequency identification (RFID) reader circuit, is presented here. First, a novel deformed microstrip rat-race circuit (RRC) is designed to take the place of traditional circulator. The microstrip device is integrated in the leakage carrier extraction circuit, which is connected in the receiver and balanced by the open-loop circuit. One of the advantages of the delicately designed system is that no need of real-time tracking to balance the variations of the amplitude and the phase of the leakage carrier. Results demonstrate that the leakage carrier with the leakage carrier extraction cancellation circuit (CECC) is improved to be 108 dB in UHF RFID narrow bands from 920 to 925 MHz and to be 117 dB at the centre frequency point. The Tx-to-Rx isolation is improved to be 48–70 dB higher than that of other cancellation circuits. The proposed leakage carrier cancellation system shows obvious improvement on the efficiency of the isolation. Both the experiment and simulation demonstrate the merits of properties of the novel designed system with the benefits of improved isolation and lower cost.

A capacitive inclination micro-sensor based on the liquid dielectric has been proposed, analysed, and simulated. The sensor structure is cylindrical and is half filled with the Silicone oil. There are three parallel plate capacitors in the structure of the inclinometer, which are formed between two ends of the cylinder. These capacitors have a common plate on one end, while other plates are formed on other end of the cylinder. The authors introduce C_out as a special function of the structural capacitors such that different external weights on three separate capacitors’ values helps obtaining linear and continuous relation for C_out versus inclination angle. Tilt application to the sensor tends to the liquid dielectric movement in the cavity and consequently variations of the structural capacitors. The authors plot analytical expressions of the capacitors and C_out versus tilt angle using MATLAB besides simulating inclinometer by COMSOL multiphysics. Extracted results from analysis and simulation are in good agreements. Proposed inclinometer has sensitivity of 8.011 fF/deg in 0–360° range. Cross-axis sensitivity of the sensor is also surveyed. Some specifications of the proposed micro-inclinometer are wide linear measurement range, high sensitivity, simplicity of the structure, and manufacturing process, which could make it attractive for different applications.

Cognitive radio network (CRN) is a promising technology to solve increasing spectrum scarcity problems in recent times. This study resolves the problem of cooperative spectrum sensing (CSS) and spectrum allocation in CRN-CSS in order to improve spectrum efficiency. A two-stage spectrum allocation scheme is initiated by grouping secondary users (SUs) with the knowledge of one-hop neighbor approach, which leads to minimised grouping time. These grouped SUs perform spectrum sensing in cooperative manner. Optimal channel assignment (OCA) process assigns channels to each SU in a group in a dynamic manner. Upon the assigned channel, SU performs spectrum sensing with the aid of the enhanced threshold energy detection (ETED) method. Finally, the available spectrum is allocated to SUs by a novel two-stage allocation approach. In this approach, SUs, which provide accurate spectrum sensing result, are given high priority for spectrum allocation. These SUs are detected through global decision making at the fusion centre (FC). A novel mining tree scheme with a spectrum agent is adopted for decision making at the FC. The neuro-fuzzy based spectrum allocation scheme in two-stage allocation supports effective spectrum allocation. An extensive experimental result exhibits promising improvements than in the previous approaches.

Multiplexer is one of the widely used logics in VLSI design. This paper presents a novel method to design the n-input Memristor-based AND and OR operations. Then, two methods are proposed to design complete and incomplete n to 1 Memristor-based multiplexers (MUXs) based on these novel Memristor-based AND and OR operations. The simulation results confirm the accuracy and functionality of the proposed methods. The comparison between n to 1 MUXs shows that the proposed n to 1 MUXs provide improvements in terms of area and speed compared to other n to 1 MUXs.

The amount of radar's raw echo data is usually very large. At the same time, synthetic aperture radar (SAR) imaging system needs rapid transpose efficiency to improve the real-time performance of the system. Therefore, modern real-time SAR system requires high-speed and large-capacity devices which are usually SDRAM chips to store raw echo data and to solve the corner turning problem by efficient matrix transpose method. By designing data interleaved patterns and controlling command cycles of SDRAM chips in a reasonable way, this paper presents a novel matrix transpose method which can be used to improve the efficiency of corner turning memory (CTM) for real-time SAR imaging system. After board-level verification, the efficiency of this new matrix transpose method can be greatly improved to >99%, which is greater than other typical SDRAM-based CTM design methods and is more suitable for real-time SAR imaging system.

One of the well-known physical attacks, i.e. differential fault analysis (DFA), can break the secret key of cryptographic device by using differential information between faulty and correct ciphertexts. Here, the authors propose a random 2-byte fault model, present a novel DFA on AES key schedule, and show how an entire AES-128 key can be cracked by using two pairs of faulty and correct ciphertexts. By inducing a random 2-byte fault in the first column of 9th round key with discontiguous rows, the authors can obtain 64 bits of AES-128 key using one pair of faulty and correct ciphertexts, two pairs of them can retrieve the entire 128-bit key without exhaustive search. The authors implement the proposed attack on HP Intel(R) Core i5-7300HQ Quad-Core 2.5 GHz CPU, 8G RAM. It takes <2 min on average to break the key. Considering the number of faulty ciphertexts, fault-induced depth, and fault model, authors’ attack is the most efficient DFA as compared to existing schemes on AES-128 key schedule.

This article suggests an evolutionary optimisation method namely symbiotic organisms search (SOS) algorithm-based area optimised designs of a nulling resistor compensation circuit and a robust bias-based complementary metal oxide semiconductor (CMOS) analogue operational amplifier (op-amp) circuit. SPICE simulator is used to validate the results obtained by using the optimisation technique SOS. The results obtained by SPICE simulation confirm that all the design specifications are accurately satisfied for both the circuits considered here. The results also prove that the SOS algorithm is superior to the formerly reported methods in terms of the gain, power dissipation, area etc., for both the individual circuits.

This study suggests an evolutionary technique namely symbiotic organisms search (SOS) algorithm based optimal designs of two different analogue very-large-scale integration circuits. The configurations considered here are nulling resistor compensation based complementary metal–oxide–semiconductor (CMOS) two-stage op-amp and two-stage CMOS op-amp with robust bias circuit. The prime goal of this work is the sizing of metal–oxide–semiconductor (MOS) transistors employing the SOS algorithm to optimise the area occupied by the individual circuit. Design results based on the SOS algorithm are authenticated with SPICE simulation. SPICE simulation results reveal that all the design specifications are firmly satisfied for both the circuits. Moreover, SPICE based results show that the SOS algorithm provides much better results compared to the earlier reported techniques regarding the gain, MOS area and power dissipation for the abovementioned op-amp circuits.

This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity-based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity-based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity-based TRNG circuit has been demonstrated. XOR gate-based post-processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm² and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity-based circuit design makes the proposed TRNG robust against reverse engineering attacks.

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

Multilayer neural networks (MNNs) have achieved excellent performance in machine-learning domain. Memristors are a possible device for implementing MNNs in hardware with efficiency and limited area. In this work, a simple model of stochastic memristors was presented first. Then, an MNN architecture based on proposed memristor model was presented. The simulation processes on stochastic memristors were elaborated. The simulation demonstrates that the MNN classification accuracy based on stochastic memristors is usually higher than that based on deterministic memristors when the dataset noise is low. The results have significant meaning to develop analogue memristive devices or memristive chips for MNN applications.

In this study, a six-track standard cell library with a multi-finger layout structure is proposed to improve the delay, energy, and area of the digital circuit design for near-threshold operation. The proposed library is optimised by using the parasitic effects of the technology and optimising the layout. To enhance the performance and energy efficiency, inverse narrow width effect has been considered in the design, whereby the minimum width of the process was used as the based width unit. To minimise the design area, the standard cell was designed in the lowest possible height with a multi-finger layout structure. The proposed library with a few basic cells was developed and characterised in 130 nm technology, which is available for synthesis and automatic place-and-route (P&R). The proposed library was analysed and compared with two eight-track multiplier layout libraries in the cell and block design level. Based on the place-and-route results of ISCAS'85 benchmark circuits, the proposed six-track library could achieve up to 27% of delay improvement, 29% energy reduction and 44% area reduction as compared to the multiplier structure library at the minimum critical path delay.

Flexibility and programmability of hearing aids are important because the algorithms applied to hearing aids should be changeable based on different types of hearing impairment and the ambient environment of the user. This paper proposes a high-performance digital signal processing (DSP) platform for a digital hearing aid system on a chip (SoC) with flexible noise estimation. The proposed DSP platform comprises several dedicated accelerators and an application-specific instruction-set processor (ASIP) to achieve flexibility. To handle complex hearing aid algorithms in real time, the main algorithms of hearing aids are executed by hardware accelerators and only environment-sensitive parts of the applied algorithms are implemented as the ASIP. Simulation results show that the proposed DSP platform can handle complex and high-performance algorithms in real time, and that it provides better quality in terms of noise handling by adapting the noise estimation algorithms suitable for the noise environment. The chip area of authors’ DSP design is 2.71 mm², and it consumes 1.3 mW at 1 V operation, 8 MHz clock frequency with a 65 nm high threshold voltage (HVT) standard cell library.

Testing is an essential process to validate the truthful functionality of logic circuits, devices, and systems. It accounts a large overhead in terms of additional hardware, time, and manpower which dramatically enhance overall cost of manufacturing. The efficacy of multiple control Fredkin (MCF) gates towards both online and offline testing paradigms is demonstrated here by exploiting their parity preserving and conservative properties. The authors introduce (i) a method of testing MCF circuits for the detection of bit-flip faults online; (ii) deterministic approaches for the identification of stuck-at, bridging, missing gate, and cross-point faults; and (iii) three test sets of size 2, n, and for the detection of these faults off-line. Experiments are performed on a set of benchmarking circuits to demonstrate the effectiveness of the proposed methods in terms of test overhead and fault coverage. Online testable circuits are formulated on account of 0.5% of overhead in terms of considered cost metrics and an average reduction up to 61% is calculated with respect to existing work in the area. The test sets show completeness for the detection of all considered fault models. Fault simulations for both the presented testing methodologies are carried out which shows 100% coverage.